Time-Interleaved ADC Cross-Correlation for Offset Calibration
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges in controlling and compensating for gain and timing mismatches, which affect their performance and throughput in high-speed applications.
Innovation Solution
A system and method that includes a signal generator, parallel ADCs, filtering components, delay adjustment components, and a cross-correlating component to determine gain error and time-offset calibration data, which are used to update the output digital signal and calibrate individual ADCs, thereby compensating for mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved architecture is used to improve ADC throughput, then sample rate increases, but gain and timing mismatches between channel ADCs worsen
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual conversion operations. The system measures gain and timing mismatches using calibration signals, then stores calibration data that is applied during normal operation to compensate for the mismatches, allowing the time-interleaved ADC to achieve high throughput while maintaining precision.
Solution Approach 2:
The patent implements feedback by using the measured calibration data to adjust and compensate for gain and timing mismatches in real-time. The system continuously monitors performance through calibration signals and applies corrective factors to the conversion results, ensuring that the high throughput of the time-interleaved architecture does not compromise measurement accuracy.
2Productivity
If multiple parallel ADCs are used to increase sample rate, then throughput improves, but device complexity increases
Solution Approach 1:
The patent merges multiple parallel ADCs into a unified time-interleaved architecture that operates as a single high-throughput converter. By coordinating the output of multiple ADCs and applying unified calibration and compensation techniques, the system achieves high sample rates while managing complexity through integrated control rather than treating each ADC as a separate complex system.
Solution Approach 2:
The patent applies universality by creating a calibration and compensation mechanism that works across all channel ADCs simultaneously. The calibration system is designed to handle multiple ADCs with a unified approach, measuring and compensating for mismatches in a way that benefits the entire time-interleaved architecture rather than requiring individual calibration for each ADC.
3Measurement precision
If calibration measurements are performed to reduce mismatches, then measurement precision improves, but time required for calibration increases
Solution Approach 1:
The patent performs calibration measurements in advance before normal conversion operations begin. By completing the time-consuming calibration process beforehand and storing the results for reuse, the system achieves high measurement precision through accurate mismatch compensation while minimizing the time lost to calibration during actual operation.
Solution Approach 2:
The patent implements periodic calibration where mismatch measurements are performed at scheduled intervals rather than continuously. This approach maintains measurement precision by regularly updating calibration data while minimizing time loss by confining calibration activities to specific periodic moments rather than interfering with continuous conversion operations.
Data Source
AI summary
Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.