Successive Approximation ADC With Cyclic DAC for Smaller, Faster Conversion
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Solution Overview
Problem
Successive approximation type A-to-D converters face challenges with high power consumption and large circuit size due to the need for a large number of capacitors in DACs, which reduces conversion speed and increases power consumption, especially in portable equipment where multiple radio systems must be integrated on a single chip.
Innovation Solution
The implementation of a successive approximation type A-to-D converter with a cyclic D-to-A converter, a comparator, and memory means that stores and reverses the output values, reducing circuit size and power consumption by using a smaller number of capacitors and flip-flops, and connecting multiple converters in parallel for high-speed conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of capacitors are used in the DAC to maintain conversion accuracy, then the accuracy is improved, but the circuit size increases and power consumption increases
Solution Approach 1:
The patent divides the conversion process into two independent stages: a first conversion stage using a first DAC with first capacitors, and a second conversion stage using a second DAC with second capacitors. This segmentation allows each stage to use fewer capacitors (reducing circuit size) while maintaining overall conversion accuracy through the combination of both stages.
Solution Approach 2:
The patent introduces a time dimension by performing conversions in sequential stages rather than simultaneously. The first conversion stage processes the input signal to produce an intermediate result, which is then processed by the second conversion stage. This temporal dimension allows accuracy to be achieved through multi-stage processing without requiring all capacitors to be present simultaneously, thus reducing circuit size.
2Measurement precision
If a large number of capacitors are used in the DAC to maintain conversion accuracy, then the accuracy is improved, but the power consumption increases
Solution Approach 1:
The conversion process is segmented into two stages, each using a separate DAC with its own set of capacitors. The total power consumption is distributed across two smaller capacitor arrays rather than one large array, reducing the instantaneous power consumption while maintaining overall conversion accuracy through the combined output of both stages.
3Measurement precision
If a large number of capacitors are used in the DAC, then the accuracy is improved, but the conversion speed decreases
Solution Approach 1:
The patent segments the conversion process into two faster, sequential stages rather than one slow, single stage. Each stage uses fewer capacitors, allowing faster charging and discharging operations. The overall conversion speed is improved because two smaller, faster operations replace one large, slower operation, while accuracy is maintained through the combination of both stages.
4Adaptability or versatility
If multiple radio systems are integrated on a single chip, then the functionality is improved, but the unit cost increases
Solution Approach 1:
The patent implements a multi-functional ADC architecture that can serve multiple radio systems on a single chip. The first and second DACs can be shared across different radio frequency modules, allowing one ADC unit to perform multiple conversion functions. This universality reduces the total number of ADC units needed, thereby reducing the unit cost while maintaining the ability to integrate multiple radio systems.
Data Source
AI summary
A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.