ADC-DAC Data Path Latency Tuning for Deterministic Timing
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Solution Overview
Problem
Existing ADC and DAC circuits in Active Electronically Scanned Arrays (AESA) systems are constrained by the requirement of hard deterministic latency, which is complex and costly, limiting the design of more economical and high-performing data converters.
Innovation Solution
Implementing data converters without the constraint of hard deterministic latency by measuring and tuning the latency of ADC and DAC data paths using loopback paths and variable latency circuits, allowing for the integration of ADC and DAC in the same integrated circuit die or package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard deterministic latency is enforced in ADC and DAC circuits, then coherent reception and transmission in AESA systems is maintained, but device complexity and cost increase
Solution Approach 1:
The patent introduces a loopback path as an intermediary mechanism that carries timing information from the ADC data path through the DAC data path and back to the ADC. This timing information serves as a mediator that enables latency measurement and tuning without requiring hard deterministic latency constraints in the original data paths, thus maintaining coherence while reducing complexity
Solution Approach 2:
The patent implements preliminary latency measurement and tuning actions through the loopback path before actual data conversion operations. By measuring and adjusting latencies in advance using the loopback mechanism, the system establishes deterministic timing relationships without needing to enforce hard deterministic latency constraints during normal operation, thereby reducing device complexity while maintaining reliability
2Measurement precision
If hard deterministic latency is enforced in ADC and DAC circuits, then timing precision is maintained, but manufacturing cost increases
Solution Approach 1:
The loopback path acts as an intermediary that enables timing precision measurement and adjustment without requiring expensive hard deterministic latency enforcement in the main data paths. The timing information traveling through the loopback provides the necessary precision data at lower cost
Solution Approach 2:
The patent implements a feedback mechanism where timing information from the loopback path is used to measure and tune latencies in the ADC and DAC data paths. This feedback loop enables automatic adjustment of timing parameters to achieve precise timing relationships without requiring costly hard deterministic latency constraints in the manufacturing process
3Device complexity
If ADC and DAC are integrated in the same die, then device complexity is reduced, but timing synchronization becomes more challenging
Solution Approach 1:
The patent merges the ADC and DAC functions into the same integrated circuit die, which simplifies the overall device structure and reduces complexity. The shared substrate and interconnect structures provide inherent timing advantages while the loopback path compensates for any synchronization challenges arising from the integration
Solution Approach 2:
The loopback path serves as an intermediary timing reference that traverses both the ADC and DAC data paths within the integrated die. This intermediary mechanism provides a common timing reference that enables precise synchronization between the integrated components, offsetting any timing challenges introduced by the close integration
Data Source
AI summary
A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.