Redundant-Bit ADC Calibration for DAC Mismatch Correction
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Solution Overview
Problem
High-resolution analogue-to-digital converters (ADCs) face limitations in power efficiency and accuracy due to intrinsic DAC mismatch and comparator offset errors, which current calibration methods either require significant overhead in area, speed, and power or introduce additional complexity, especially when implemented on-chip.
Innovation Solution
A low-power, fully automated on-chip background calibration method that utilizes redundancy to detect and correct DAC mismatch errors by exploiting the (N+1) bit code redundancy, performing an additional comparison cycle, and tuning switchable binary scaled calibration capacitors to eliminate mismatch errors, thereby reducing overhead and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional calibration methods are used to correct DAC mismatch, then accuracy is improved, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent applies preliminary action by performing calibration during the normal conversion process rather than as a separate operation. The (N+1)th bit code from the binary search algorithm is utilized to directly detect DAC mismatch errors without requiring additional calibration cycles or separate calibration modes, thereby reducing complexity while maintaining accuracy improvement
Solution Approach 2:
The system uses its own redundant (N+1)th bit code output from the search logic as the calibration trigger, making the calibration process self-service. The normal conversion operation generates the calibration information needed, eliminating the need for external calibration equipment or complex dedicated calibration circuitry
2Measurement precision
If adaptive learning algorithms are used for DAC correction, then accuracy is improved, but power consumption and area overhead increase
Solution Approach 1:
The patent extracts the essential calibration function from complex adaptive learning algorithms. By using the redundant (N+1)th bit code to directly indicate DAC mismatch errors, it separates the calibration trigger generation from the complex digital processing required by LMS algorithms, thereby reducing power consumption while maintaining correction capability
Solution Approach 2:
The patent uses a simple, low-power calibration trigger mechanism based on the existing redundant bit code rather than expensive, power-hungry adaptive learning algorithms. The calibration is performed using basic comparator and switch logic instead of complex digital signal processing, achieving correction with minimal power overhead
3Measurement precision
If off-chip calibration is performed, then accuracy is improved, but loss of time and automation level decrease
Solution Approach 1:
The patent merges the calibration function with the normal ADC conversion operation. The calibration trigger is generated from the (N+1)th bit code during the regular binary search process, and the calibration correction is applied within the same conversion cycle, eliminating separate calibration time and achieving full automation
Solution Approach 2:
The redundant (N+1)th bit code serves multiple functions: it is used for normal N-bit conversion output and simultaneously serves as the calibration trigger. This multi-functionality allows the system to perform both conversion and calibration without additional time overhead, achieving automated on-chip calibration
Data Source
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AI summary
The present invention relates to a method for calibrating an analog-to-digital converter, ADC, converting an input voltage signal into a N bit output signal representing said input voltage signal. The method comprises : - sampling the input voltage signal applied to the analog-to-digital converter, - comparing the sampled input voltage signal with an output signal of a feedback digital-to-analogue converter, DAC, (40), - determining in a search logic block (30) of the ADC a (N+1) bit code representation for the comparison result, the (N+1) bit code yielding the N bit output signal, - on detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for one of the most significant bits of the (N+1) bit code by replacing said (N+1) bit code by an alternative (N+1) bit code which yields the same N bit output signal, performing an additional comparison cycle using said alternative (N+1) bit code, determining, using the comparison results of said additional comparison cycle and of the preceding (N+1)th cycle, the sign of a DAC capacitor mismatch error, tuning a set of programmable binary scaled calibration capacitors (41) in parallel to a capacitor corresponding to said one of the most significant bits of said (N+1) bit code for which the calibration is performed.