Sigma-Delta ADC Feedback DAC Pulse Shaping for Jitter Control
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Solution Overview
Problem
Sigma-delta analog-to-digital converters (ADCs) face challenges with clock jitter sensitivity and high DC power consumption due to the characteristics of digital-to-analog converters (DACs) used in their conversion feedback paths, which compromise design and performance.
Innovation Solution
A DAC with a current pulse shaping mechanism, utilizing a capacitor circuit pre-charged to a reference voltage and a resistive circuit that varies resistance during each feedback cycle to control the current pulse shape, ensuring consistent charge transfer and reduced peak currents, thereby minimizing clock jitter sensitivity and DC current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a switched current source DAC is used to generate conversion feedback signal, then the charge transfer consistency is improved, but the clock jitter sensitivity increases and DC power consumption increases
Solution Approach 1:
The capacitor is pre-charged to a reference voltage level before the feedback cycle begins. This preliminary charging action ensures that the capacitor has the exact voltage needed to generate the precise charge transfer required, eliminating the need for high peak currents during the feedback cycle and reducing clock jitter sensitivity.
Solution Approach 2:
The DAC operates by periodically charging the capacitor to a reference voltage at the beginning of each feedback cycle and then discharging it through a resistive circuit. This periodic charge-discharge cycle creates a controlled current pulse that maintains consistent charge transfer while reducing peak current requirements and DC power consumption.
2Object-affected harmful factors
If a capacitor-based DAC is used to reduce clock jitter sensitivity, then the clock jitter insensitivity is improved, but the peak current increases and DC power consumption increases
Solution Approach 1:
The capacitor is pre-charged to a reference voltage level before the feedback cycle begins. This preliminary charging action ensures that the capacitor has the exact voltage needed to generate the precise charge transfer required, eliminating the need for high peak currents during the feedback cycle and reducing clock jitter sensitivity.
Solution Approach 2:
The resistive circuit dynamically adjusts its resistance during the feedback cycle to control the discharge current profile. By varying the resistance, the circuit shapes the current pulse to achieve the desired charge transfer while maintaining lower peak currents and reducing DC power consumption compared to traditional switched current source DACs.
3Speed
If high peak currents are used in DAC, then the charge transfer speed is improved, but the gain-bandwidth requirements and slew-rate requirements of integrating amplifier increase
Solution Approach 1:
The capacitor is pre-charged to a reference voltage level before the feedback cycle begins. This preliminary charging action ensures that the capacitor has the exact voltage needed to generate the precise charge transfer required, eliminating the need for high peak currents during the feedback cycle and reducing clock jitter sensitivity.
Solution Approach 2:
The DAC operates by periodically charging the capacitor to a reference voltage at the beginning of each feedback cycle and then discharging it through a resistive circuit. This periodic charge-discharge cycle creates a controlled current pulse that maintains consistent charge transfer while reducing peak current requirements and DC power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved clock jitter insensitivity and reduced DC current consumption, along with lower gain-bandwidth and slew-rate requirements for the integrating amplifier, enhancing the overall performance of sigma-delta ADCs.
Implementation Method 1
a capacitor circuit configured to be pre-charged to a reference voltage for each feedback cycle of the ADC
Implementation Method 2
a resistive circuit for transferring charge between the capacitor circuit and a loop filter of the ADC in each feedback cycle
Data Source
AI summary
A method and apparatus taught herein provide a digital-to-analog converter (DAC) for use in a conversion feedback path of a sigma-delta type analog-to-digital converter (ADC). The DAC uses current pulse shaping to generate a conversion feedback signal in each feedback cycle of the ADC that provides a consistent charge transfer for accurate digital conversion and has a controlled current pulse shape. In one or more embodiments, the DAC includes a capacitor circuit for charge storage and transfer and a (series) resistive circuit having variable resistance for current pulse shape control. In at least one embodiment, current pulse control limits a peak current of the conversion feedback signal, thereby reducing DC power consumption and gain-bandwidth (GBW) and slew rate requirements of the ADC's integration amplifier, and limiting residual (ending) current in each feedback cycle, which yields commensurate gains in (feedback cycle) clock jitter insensitivity.