ADC/DAC Built-In Self-Test for Converter Reliability Checks

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Solution Overview

Problem

Semiconductor integrated circuits used in critical applications like autonomous driving systems require high reliability and safety, but existing data converters lack efficient testing methods to ensure normal operation, particularly in high-stakes environments where abnormal operation can cause danger.

Innovation Solution

Incorporating a built-in self-test circuit within the semiconductor integrated circuit that generates test signals and determines normality by converting test patterns through both analog-to-digital and digital-to-analog converters, enabling efficient testing and fault detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a built-in self-test circuit is incorporated into the semiconductor integrated circuit, then the reliability and safety of data converters are improved through efficient testing and fault detection, but the device complexity increases due to the additional test circuit components

Engineering Contradiction:
Improvereliability and safety of data convertersVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the self-test functionality with the existing data converter circuitry by incorporating a built-in self-test circuit that shares the same analog-to-digital converter and digital-to-analog converter resources. This combining approach enables reliability testing without adding completely separate test equipment, thus improving reliability while minimizing the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor integrated circuit performs self-testing through the built-in self-test circuit that generates test signals and evaluates the normality of data converters internally. This self-service mechanism eliminates the need for external testing equipment during operation, improving reliability through continuous monitoring while avoiding the complexity of external test systems.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If comprehensive testing of data converters is performed using external testing equipment, then the measurement precision and fault detection capability are improved, but the productivity and ease of operation deteriorate due to complex testing procedures and time consumption

Engineering Contradiction:
Improvefault detection capabilityVSAvoidproductivity and ease of operation
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The built-in self-test circuit enables the data converter to perform comprehensive fault detection autonomously without external testing equipment. The circuit generates test signals, processes them through the data converter paths, and determines normality internally, maintaining high measurement precision while dramatically improving productivity by eliminating complex external testing procedures.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The self-test circuit performs testing operations in advance or during idle periods without requiring external equipment setup. By having the testing capability built-in and ready to execute, the system can quickly assess data converter status without the time-consuming setup and operation of external testing equipment, thus improving both measurement precision and productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11698410B2Semiconductor integrated circuit and method of testing the same
Publication Date: 2023.07.11 SAMSUNG ELECTRONICS CO LTD
  • US11698410B2 patent drawing
  • US11698410B2 patent drawing
  • US11698410B2 patent drawing

AI summary

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.