Iterative ADC-DAC Interleave Calibration for Spur Reduction
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Solution Overview
Problem
High sample rate analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) face errors due to offset, gain, and timing mismatches when interleaved, leading to errors in in-phase and quadrature (IQ) data and spurs in the frequency spectrum.
Innovation Solution
A circuit and method for calibrating ADCs and DACs using a DAC-generated calibration signal, filtered to remove spurs, which is then used by the ADC to calculate interleave calibration factors. This process is iteratively repeated until performance metrics, such as spur-free dynamic range (SFDR), are within a predetermined range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADCs are interleaved to achieve higher sample rates, then the sampling speed is improved, but offset, gain, and timing errors between the ADCs result in spurs in the frequency spectrum
Solution Approach 1:
The patent applies preliminary calibration action before normal operation. A calibration sequence is generated and processed through the interleaved ADCs to determine calibration factors that correct timing, offset, and gain errors. This preliminary calibration establishes correction parameters that are then applied during subsequent signal processing, preventing spurs from appearing in the frequency spectrum while maintaining the high sampling speed benefit of interleaving
Solution Approach 2:
The patent implements a feedback mechanism where the output of the interleaved ADCs is fed back through a calibration process. The calibration sequence output is analyzed to determine actual timing and gain characteristics, which then feed back as calibration factors to adjust the ADC operation. This closed-loop feedback continuously corrects the harmful effects of interleaving mismatches, eliminating spurs while preserving high-speed sampling capability
2Measurement precision
If conventional calibration circuits use optimized external signals and complex calculations with various filters, then calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the ADCs themselves multi-functional by using them both for normal signal conversion and for self-calibration. The same ADCs that convert signal data are also used to process the calibration sequence and determine calibration factors. This eliminates the need for separate dedicated calibration circuits, reducing device complexity while maintaining calibration accuracy through the ADCs' inherent high precision
Solution Approach 2:
The calibration system performs self-service by using its own resources - the interleaved ADCs generate and process their own calibration sequences and determine their own calibration factors without requiring external calibration equipment. This self-calibration approach reduces external dependencies and circuit complexity while achieving accurate calibration through the ADCs' internal processing capabilities
Data Source
AI summary
A circuit and method for calibrating ADCs and DACs generates a calibration signal by a DAC; filters spurs from the calibration signal from the DAC to generate a filtered calibration signal; calculates ADC interleave calibration factors to improve performance metrics of the ADC, responsive to the filtered calibration signal; receives the calibration signal from the DAC and calculates DAC interleave calibration factors; generates a calibration signal with improved performance metrics, responsive to the DAC interleave calibration factors received from the ADC; and repeats the process until the performance of the ADC and DAC are within a predetermined range.