Split-Capacitor ADC Calibration for DAC Weighting Mismatch
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Solution Overview
Problem
In split capacitor array analog-to-digital converters (SCA ADCs), the requirement for precise matching of capacitors leads to increased chip area and power consumption due to larger unit capacitance, which in turn necessitates a stronger driving circuit, thereby increasing area and power consumption further.
Innovation Solution
A method and apparatus for evaluating capacitor weighting in a digital-to-analog converter (DAC) using a calibration logic circuit, a comparator, and a switch device to measure and calculate group weighting values of capacitors, allowing for equivalent weighting values to be obtained, thereby reducing the need for precise capacitor matching and minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If larger unit capacitance is used to satisfy capacitor matching requirements, then linearity is improved, but chip area and power consumption increase
Solution Approach 1:
The capacitor array is divided into multiple sub-arrays, each with fewer capacitors. This segmentation allows each sub-array to use smaller unit capacitance while the collective arrangement maintains the required weighting precision, thereby reducing chip area while preserving linearity.
Solution Approach 2:
A calibration logic circuit is introduced as an intermediary component that measures and compensates for capacitor weighting deviations. This mediator enables the system to achieve precise linearity correction without requiring physically large capacitors, thus resolving the contradiction between matching precision and area consumption.
2Manufacturing precision
If larger unit capacitance is used to satisfy capacitor matching requirements, then linearity is improved, but power consumption increases
Solution Approach 1:
By segmenting the capacitor array into multiple sub-arrays with smaller unit capacitances, the total charge storage requirement is distributed across more components. This reduces the power consumption of the driving circuit while maintaining the overall precision through the segmented architecture.
Solution Approach 2:
The calibration logic circuit acts as a mediator that compensates for precision losses from smaller capacitors. It measures actual weighting values and applies corrections, enabling small-capacitor designs to achieve the same linearity as large-capacitor designs, thereby reducing power consumption without sacrificing precision.
3Manufacturing precision
If stronger driving circuit is used to drive larger capacitors, then capacitor matching is improved, but chip area and power consumption increase
Solution Approach 1:
The driving circuit is segmented to drive multiple sub-arrays of smaller capacitors instead of a single large capacitor array. This segmentation reduces the power and area requirements of the driving circuit while maintaining the ability to achieve precise capacitor matching through the distributed architecture.
Solution Approach 2:
The calibration logic circuit serves as an intermediary that compensates for the reduced driving capability. It measures weighting deviations and applies digital corrections, enabling the system to achieve precise capacitor matching even with weaker, lower-power driving circuits that can handle smaller capacitors.
Data Source
AI summary
A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.