ADC Debounce Control for Early Abort of Unstable Conversions

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Solution Overview

Problem

Analog-to-digital converters face challenges in accurately converting rapidly changing analog signals, leading to misjudgments and incorrect system operations due to interference, and this inefficiency increases power consumption.

Innovation Solution

An analog-to-digital conversion circuit with a debounce controller that integrates conversion bits and checks against threshold ranges to abort the conversion process when data exceeds normal limits, preventing incorrect outputs and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the analog-to-digital converter continues converting during rapid signal changes, then the conversion process completes, but misjudgments and incorrect outputs occur due to interference

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion completion rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The debounce controller performs preliminary detection of signal stability before the ADC completes full conversion. By checking whether the analog signal remains within a normal range during conversion, the system can abort unstable conversions before they produce incorrect digital outputs, thus preventing misjudgments while maintaining overall conversion efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback control by continuously monitoring the analog signal during conversion and using the debounce controller to detect abnormal changes. When the signal exceeds the normal range, the debounce controller generates an abort signal to stop the conversion, creating a closed-loop control mechanism that ensures conversion accuracy without sacrificing productivity.

Inventive Principle:
Principle #23Feedback

2Productivity

If the analog-to-digital converter processes all signals, then conversion throughput is maintained, but power consumption increases due to unnecessary conversions of unstable signals

Engineering Contradiction:
Improveconversion throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The debounce controller performs a partial check of the analog signal during the conversion process rather than requiring full conversion completion. By detecting abnormal signal changes early and aborting the conversion, the system performs only the necessary portion of the conversion operation, reducing power consumption for unstable signals while maintaining throughput for stable signals.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If higher resolution conversion is performed, then measurement precision improves, but more clock cycles are required increasing conversion time

Engineering Contradiction:
Improveconversion resolutionVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The debounce controller performs preliminary detection during the conversion process to determine signal stability. When instability is detected, the conversion is aborted early, avoiding the time penalty of completing full high-resolution conversion for unstable signals. This selective approach maintains measurement precision for stable signals while reducing conversion time for unstable ones.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12587200B2Analog-to-digital conversion circuit and method
Publication Date: 2026.03.24 NUVOTON
  • US12587200B2 patent drawing
  • US12587200B2 patent drawing
  • US12587200B2 patent drawing

AI summary

An analog-to-digital conversion circuit is provided. The analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) and a debounce controller. The ADC is configured to sequentially convert an analog input signal into a plurality of conversion bits in response to a plurality of cycles of a clock signal. The debounce controller is configured to sequentially receive the conversion bits in response to each of the cycles of the clock signal. In each of the cycles, the debounce controller is configured to integrate the received conversion bits into conversion data and to determine whether the conversion data exceeds a normal range. When the conversion data exceeds the normal range, the debounce controller is configured to provide an abort signal to the analog-to-digital converter, so that the analog-to-digital converter stops converting the analog input signal.