ADC Decimation Control for High-Frequency Waveform Storage
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Solution Overview
Problem
Existing AD conversion devices face challenges in reducing the storage capacity of the storage unit due to the inclusion of time stamps in waveform data, which inhibits capacity reduction, especially when handling high-frequency signals.
Innovation Solution
An AD conversion device that includes a control unit to monitor high-frequency components in the analog signal, setting high-speed and decimation regions, and uses a decimation rate of 1/N0 to store sampling data, associating it with decimation bit information, thereby reducing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency is increased to handle high-frequency signals, then the measurement precision is improved, but the storage capacity requirement increases
Solution Approach 1:
The patent applies dynamic decimation where the decimation rate is not fixed but changes based on signal characteristics. The system dynamically adjusts between normal decimation (1/N0) and high-speed sampling mode when high-frequency components are detected, allowing the storage system to adapt to varying signal requirements and reduce overall storage capacity needs.
Solution Approach 2:
The system changes the sampling parameter (decimation rate) based on the detected signal frequency characteristics. When high-frequency components are present, the system switches to a different sampling mode that captures essential high-frequency information while using fewer stored samples, thereby reducing storage capacity requirements while maintaining measurement precision.
2Reliability
If all sampling data is stored without decimation, then the reliability is improved, but the storage capacity increases
Solution Approach 1:
The patent applies different storage qualities to different portions of the sampling data. Normal sampling data is decimated at rate 1/N0, while data containing high-frequency components is stored at full resolution. This local differentiation ensures that only the critical portions requiring high reliability are stored completely, while other portions use reduced storage, thereby maintaining overall data reliability while reducing total storage capacity.
Solution Approach 2:
The decimation control unit acts as an intermediary that selectively identifies and flags data containing high-frequency components. This intermediary mechanism determines which data portions require full storage for reliability and which can be decimated, enabling the system to maintain data completeness for critical information while reducing overall storage requirements through intelligent selection.
3Quantity of substance
If decimation is applied to reduce storage capacity, then the storage capacity is reduced, but the device complexity increases
Solution Approach 1:
The decimation control unit automatically detects high-frequency components in the sampling data and autonomously determines the appropriate storage mode without requiring external intervention or complex external control circuits. The system self-regulates the decimation process based on real-time signal analysis, reducing the need for additional complex peripheral control circuitry while maintaining effective storage capacity reduction.
4Measurement precision
If time stamps are included in waveform data for time management, then the measurement precision is improved, but the storage capacity increases
Solution Approach 1:
The patent extracts and separates the time management function from the main sampling data storage. Instead of including time stamps with every sampling point, the system uses a separate counter that operates independently to track time information. This extraction eliminates the need to store time stamps in the main data buffer, reducing storage capacity requirements while maintaining accurate time measurement capabilities through the separate counter mechanism.
Data Source
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AI summary
An AD conversion device (1) includes an AD converter (3) that outputs an analog signal as sampling data for every sampling point based on a sampling frequency, a control unit (4), and a storage unit (5), the control unit (4) includes a buffer memory (42) which temporarily stores the sampling data from the AD converter (3) in time series and from which the sampling data is read out in time series, and a decimation control unit (41), the decimation control unit (41) sets a region having a plurality of sampling points including a sampling point in the sampling data from the AD converter (3), containing a high-frequency component, and sampling points before and after that sampling point, as a high-speed sampling region, sets a region other than the high-speed sampling region as a decimation region in which sampling is performed at a decimation rate of 1/No, outputs a write-enable signal indicating write-enabled for the selected sampling data in the decimation region and the sampling data in the high-speed sampling region, and outputs decimation bit information indicating whether the sampling data is the sampling data of the decimation region or the sampling data of the high-speed sampling region, and the storage unit (5) stores the sampling data stored in the buffer memory (42) in association with the decimation bit information from the decimation control unit (41), in response to the write-enable signal indicating write-enabled from the decimation control unit (41).