Time-Interleaved ADC Timing Compensation Using Adaptive Decorrelation
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Solution Overview
Problem
Time interleaved analog-to-digital converters (ADCs) experience timing mismatches that generate undesirable blocker signals due to phase differences in clock signals, degrading the performance of communication systems by aliasing these signals onto desired frequencies, which existing technologies fail to effectively compensate for without complex analog or timing circuitry.
Innovation Solution
A method and system utilizing a symmetric adaptive decorrelation algorithm to estimate and compensate for timing mismatches in time interleaved ADCs by determining complex coupling coefficients between desired and blocker signals, allowing for digital domain cancellation of these signals using multi-tap filters or multipliers, without requiring complex analog circuitry, and employing calibration tones for foreground estimation and actual RF signals for background compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex analog or timing circuitry is used to compensate for timing mismatches, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog timing circuitry with digital signal processing techniques. Specifically, it uses digital filters and algorithms to estimate and compensate for timing mismatches between ADC paths, substituting mechanical/analog timing correction mechanisms with software-based digital processing that achieves the same timing precision without the complexity of analog circuitry
Solution Approach 2:
The patent changes the approach from correcting timing parameters in the analog domain to estimating and compensating timing mismatches in the digital domain. By using digital filters to estimate coupling coefficients and applying digital compensation algorithms, the system maintains timing precision while avoiding complex analog timing circuitry
2Device complexity
If timing offsets are not compensated, then device complexity is reduced, but signal quality deteriorates due to blocker signals
Solution Approach 1:
The patent extracts and separates the blocker signals from the desired signal in the digital domain. By using digital filters to estimate the coupling coefficients between ADC paths, the system identifies and isolates the harmful blocker signals generated by timing mismatches, then applies compensation to remove them while keeping the overall device structure simple
Solution Approach 2:
The patent converts the harmful effect of timing mismatches into a measurable parameter that can be compensated. By using the blocker signals generated by timing offsets as information sources for estimation algorithms, the system determines coupling coefficients that characterize the mismatch, then uses this information to apply digital compensation that eliminates the harmful effects while maintaining circuit simplicity
3Device complexity
If digital domain compensation is used instead of analog circuitry, then device complexity is reduced, but measurement precision may worsen
Solution Approach 1:
The patent performs preliminary estimation of timing mismatches using digital filters before applying compensation. By first estimating the coupling coefficients between ADC paths using received signals and digital filtering techniques, the system prepares accurate timing offset information in advance, ensuring measurement precision is maintained while using simpler digital circuitry
Solution Approach 2:
The patent employs feedback mechanisms where the estimated coupling coefficients from digital filtering are continuously used to adjust and refine the compensation applied to ADC paths. This feedback loop ensures that timing offset estimation accuracy is maintained through iterative digital processing, achieving precision comparable to analog methods while using simpler digital circuitry
Data Source
AI summary
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may include a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.