Image Sensor ADC Delay Compensation Without High-Speed Counters
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Solution Overview
Problem
CMOS image sensors in consumer devices face challenges in increasing operating speed without increasing clock speed, particularly due to high power consumption from high-speed counter operations required for compensating fixed pattern noise.
Innovation Solution
An analog-to-digital converter (ADC) is designed with a comparator, delay circuit, compensator circuit, and latch circuit to compare pixel signals with a ramp signal, measure signal periods, and generate delay select signals, allowing for increased operating speed without raising clock speed by delaying signals by a calculated time period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a CDS circuit including a counter is used to compensate for pixel variations, then compensation accuracy is improved, but power consumption increases due to high-speed counter operations
Solution Approach 1:
The patent replaces the high-speed counter (mechanical/electrical counting mechanism) with a time-delay based compensation method. Instead of using a counter to track and compensate pixel variations, the invention uses delay circuits to introduce precise time delays to reference signals, enabling correlation double sampling without requiring high-speed counting operations. This substitution dramatically reduces power consumption while maintaining compensation accuracy.
Solution Approach 2:
The patent changes the operating parameter from high-speed counter operations to controlled time-delay parameters. By adjusting delay amounts in delay circuits based on measured signal periods, the system achieves effective compensation through parameter optimization rather than high-speed mechanical counting, thereby reducing power consumption while maintaining measurement precision.
2Productivity
If the clock speed is increased to improve operating speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic time-delay adjustment based on measured signal periods. The delay circuits adapt their delay amounts according to the actual period of comparison signals, allowing the system to optimize its operating speed dynamically without requiring a fixed high clock frequency. This dynamic adaptation enables efficient operation at lower power consumption levels while maintaining high productivity.
Solution Approach 2:
The patent implements a feedback mechanism where the period of comparison signals is measured and used to control the delay amounts in delay circuits. This feedback loop enables the system to automatically adjust its timing parameters to achieve optimal operating speed without increasing clock frequency, thereby improving productivity while controlling power consumption.
Data Source
AI summary
An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal includes a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal to output a delay select signal to the delay circuit based on the measured period, the delay select signal delaying the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.