ADC Delay Calibration for High-Speed Linearity Correction
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Solution Overview
Problem
High-speed analog to digital converters (ADCs) used in RF sampling receivers face challenges with non-linearity, leading to large power dissipation and area requirements, especially at giga-samples per second (GSPS) sampling rates.
Innovation Solution
A calibration scheme for ADCs involving a voltage-to-delay (VD) block and a backend ADC with multiple stages, utilizing a calibration engine to measure and store optimal delay values for each stage to correct non-linearity, employing a lookup-table approach to achieve linear operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed ADC operation is implemented to achieve GSPS sampling rates, then sampling speed is improved, but non-linearity increases and power dissipation increases
Solution Approach 1:
The patent applies preliminary action by performing delay calibration before the ADC conversion process. The calibration engine pre-determines optimal delay values for each stage by minimizing error counts, and these calibrated delay values are stored for use during actual conversion. This preliminary calibration ensures that the ADC operates with optimal timing parameters, reducing non-linearity effects at high sampling rates without requiring complex real-time correction mechanisms.
2Reliability
If traditional linear ADC design is used to maintain linearity, then manufacturing precision is improved, but power dissipation and area requirements increase
Solution Approach 1:
The patent employs parameter changes by transforming the ADC from a purely analog linear conversion process to a hybrid approach that incorporates digital delay calibration. The key parameter change is in the timing/delay parameters of each conversion stage, which are optimized through the calibration engine. This allows the ADC to achieve linear operation at lower power consumption by using digitally controlled delay elements instead of requiring fully linear analog circuitry throughout, thereby reducing power dissipation while maintaining linearity.
3Speed
If multi-stage ADC architecture is implemented to improve performance, then sampling speed is improved, but device complexity increases
Solution Approach 1:
The patent implements feedback through the calibration engine that measures error counts from each stage and uses this information to optimize delay values. The calibration process creates a feedback loop where the output of each stage is evaluated and used to adjust the timing parameters of subsequent stages. This feedback mechanism allows the multi-stage architecture to be tuned for optimal performance, reducing the negative impact of complexity by ensuring each stage contributes effectively to the overall conversion process.
Data Source
AI summary
In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.