ADC Calibration Using Voltage-to-Delay Lookup Correction
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Solution Overview
Problem
High-speed analog to digital converters (ADCs) used in RF sampling receivers face challenges in correcting non-linearity, which affects their performance and requires complex algorithms and hardware, leading to high power and area requirements, especially at giga-samples per second (GSPS) speeds.
Innovation Solution
The implementation of a voltage-to-delay (VD) block coupled with a backend ADC and a calibration engine that generates a delay signal, measures error counts, and stores delay values to minimize non-linearity, allowing the ADC to operate as a linear high-speed converter without complex algorithms or hardware, using a lookup-table approach to correct non-linearities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex algorithms and hardware are used to correct non-linearity in high-speed ADCs, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing correction values in a lookup table during a calibration phase. The calibration engine pre-computes the relationship between input codes and non-linearity errors, storing these corrections in memory. During normal high-speed operation, the ADC simply retrieves pre-computed correction values from the lookup table using the input code as an address, avoiding real-time complex calculations and achieving linearity correction with minimal additional hardware complexity.
2Measurement precision
If complex algorithms and hardware are used to correct non-linearity in high-speed ADCs, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The calibration engine performs power-intensive computations during an initial calibration phase to pre-compute correction values, which are then stored in a lookup table. During normal high-speed ADC operation, the system only performs simple memory read operations to retrieve correction values, dramatically reducing real-time power consumption while maintaining linearity correction accuracy.
Solution Approach 2:
The patent creates a simplified copy of the correction function in the form of a lookup table. Instead of implementing the complex non-linearity correction algorithm in real-time hardware, the system stores pre-computed correction results in memory and retrieves them during operation. This copying approach trades initial calibration computation for minimal real-time power consumption.
3Measurement precision
If complex algorithms and hardware are used to correct non-linearity in high-speed ADCs, then measurement precision is improved, but area requirements increase
Solution Approach 1:
The patent implements non-linearity correction by copying pre-computed correction values into a lookup table stored in memory. This approach replaces the need for complex real-time correction hardware with a simple memory structure that can be efficiently implemented using standard digital logic and memory cells, significantly reducing the hardware area required for linearity correction in high-speed ADCs.
4Productivity
If high-speed operation is implemented in ADCs, then productivity is improved, but measurement precision deteriorates due to non-linearity
Solution Approach 1:
The patent implements feedback by using the ADC's own output code to index into a lookup table and retrieve the corresponding non-linearity correction value. The correction value is fed back to adjust the output, compensating for non-linearity errors. This feedback mechanism operates at high speeds because it uses simple memory read operations rather than complex real-time calculations, allowing the ADC to maintain both high sampling speed and high measurement precision.
Data Source
AI summary
In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.