ADC Sampling Circuit Using Difference Sampling for Low Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog-to-digital converter (ADC) circuits face challenges with noise sources such as kT/C sampling noise, noise coupling, and amplifier thermal noise, which are inversely proportional to sampling capacitor size, making larger capacitors difficult to drive and occupy significant die area.
Innovation Solution
The proposed solution involves an ADC circuit methodology that includes a first capacitor coupled to both the ADC input and converter circuit, where a switch is opened to decouple the capacitor from bias voltage, sampling an amplified difference signal between an estimated and actual input signal, and adjusting the capacitor based on digital output to reduce noise, allowing for smaller capacitors and reduced die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If larger sampling capacitors are used to reduce kT/C sampling noise, then noise performance is improved, but die area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by sampling the analog input signal before the actual conversion sampling instance. This pre-sampling allows the system to predict and compensate for signal variations, enabling the use of smaller capacitors while maintaining noise performance. The early sampling captures the signal state in advance, and this information is used to adjust the conversion process, thereby reducing the capacitor size requirement.
Solution Approach 2:
The patent implements feedback by using the pre-sampled signal to adjust and optimize the main sampling process. The system continuously monitors the signal characteristics and adjusts the conversion parameters accordingly, allowing smaller capacitors to achieve the same noise performance as larger capacitors would provide in a conventional system without feedback adjustment.
2Measurement precision
If larger sampling capacitors are used to reduce kT/C sampling noise, then noise performance is improved, but power consumption increases
Solution Approach 1:
By performing preliminary sampling of the analog input signal before the conversion sampling, the system can predict signal behavior and optimize the conversion process. This allows the use of smaller capacitors that consume less power during switching and charging operations, while the preliminary sampled data compensates for any noise that would otherwise require larger capacitors to suppress.
Solution Approach 2:
The feedback mechanism uses information from the pre-sampled signal to adjust the conversion process dynamically. This optimization allows the system to maintain high noise performance with smaller capacitors, directly reducing the power consumption associated with charging and discharging large capacitor values during the conversion process.
3Measurement precision
If larger sampling capacitors are used to reduce noise, then noise performance is improved, but the capacitors become difficult to drive
Solution Approach 1:
The preliminary sampling of the analog input signal provides advance information about the signal characteristics. This allows the system to prepare appropriate drive signals and voltage levels before the actual conversion sampling, making it easier to drive the smaller capacitors while maintaining the noise performance that would otherwise require larger capacitors.
Data Source
AI summary
Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.