Pipeline ADC Stage Calibration Using Dither Capacitors for Gain Error
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Solution Overview
Problem
Pipeline analog-to-digital converters (ADCs) face challenges in achieving high resolution with low power dissipation due to gain errors caused by capacitor mismatches and finite low-frequency gain, which are not accurately corrected by existing calibration methods.
Innovation Solution
A switching scheme is employed during calibration mode to determine calibration coefficients for each stage of the pipeline ADC, using a sampling capacitor with multiple sub-capacitors connected to different reference voltages to measure output voltages and calculate coefficients that account for gain errors, enabling accurate correction during operational mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If digital calibration is used to correct gain errors in pipeline ADC stages, then manufacturing precision is improved, but device complexity increases due to additional calibration circuits and procedures
Solution Approach 1:
The calibration system uses the ADC's own operational output to perform self-calibration. The calibration circuit measures the actual output code of the ADC during normal operation and automatically calculates correction values, eliminating the need for external calibration equipment and reducing overall system complexity.
Solution Approach 2:
The invention changes the calibration approach from measuring physical capacitor values to measuring the functional output parameter (ADC output code). By calibrating based on the actual digital output rather than analog component parameters, the system simplifies the calibration process while improving accuracy.
2Measurement precision
If multiple voltage measurements are taken during calibration mode, then measurement precision is improved for determining calibration coefficients, but loss of time increases due to extended calibration duration
Solution Approach 1:
The system performs preliminary measurements of the ADC output code at different input voltage levels during calibration mode before computing the final calibration coefficients. These preliminary measurements are cached and reused in the coefficient calculation, avoiding redundant measurements and reducing total calibration time.
Solution Approach 2:
The invention replaces time-consuming iterative measurement processes with a direct computational approach. By using a predetermined number of measurements at specific input levels and applying a closed-form calculation algorithm, the system eliminates the need for iterative refinement that would consume additional time.
3Manufacturing precision
If capacitor mismatches are reduced to minimize gain errors, then manufacturing precision is improved, but loss of substance increases due to additional capacitor elements and layout area
Solution Approach 1:
The invention extracts the calibration function from the physical capacitor structure itself. Instead of relying on precise capacitor matching, the system measures the actual gain error through ADC output code and applies a digital correction factor, effectively separating the gain correction function from the analog capacitor network.
Solution Approach 2:
The calibration process creates a digital copy or model of the actual gain error through measurement, then uses this digital representation to compute correction coefficients. This digital model allows correction without requiring physical modification or additional analog components.
Data Source
AI summary
A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage.