Successive Approximation ADC Dither Removal for Lower DNL
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Solution Overview
Problem
Analog to digital converters face challenges in achieving good linearity and resolution due to differential non-linearity errors, which are exacerbated by the need for additional hardware and delay in post-conversion dither correction processes.
Innovation Solution
Incorporating redundancy into the converter, such as non-binary weighting and additional bits, allows dither to be applied only during significant bit trials and removed before less significant bit conversions, eliminating the need for additional processing and hardware to correct dither offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If post-conversion dither correction is implemented using additional digital hardware, then differential non-linearity errors are reduced, but device complexity increases and conversion time increases due to processing delay
Solution Approach 1:
The patent extracts the dither correction function from the post-conversion digital domain and integrates it into the analog conversion process itself. By applying dither during the analog-to-digital conversion and removing it before completion, the need for additional digital hardware to correct DNL errors is eliminated, while still achieving the desired reduction in differential non-linearity.
Solution Approach 2:
The patent applies dither during the conversion process itself rather than correcting it after conversion. The dither is applied to the analog input signal during the conversion process and removed before the conversion completes, which is a preliminary action that prevents DNL errors from occurring in the first place rather than correcting them afterward.
2Manufacturing precision
If post-conversion dither correction is implemented, then differential non-linearity errors are reduced, but conversion time increases due to processing delay
Solution Approach 1:
The dither is applied and removed during the conversion process itself, before the conversion completes. This preliminary action ensures that the dither correction is integrated into the conversion timing, eliminating any additional processing delay that would occur if correction were applied after conversion.
Solution Approach 2:
The conversion process continues uninterrupted with the dither applied throughout the conversion. The useful action of converting the analog signal to digital continues without interruption, and the dither removal occurs seamlessly as part of the conversion process rather than as a separate post-processing step.
3Manufacturing precision
If dither is applied during all bit trials including less significant bits, then differential non-linearity errors are further reduced, but conversion time increases
Solution Approach 1:
The patent applies dither selectively during the bit trials for significant bits rather than uniformly across all bits. This local quality approach focuses the dither application where it is most needed (during significant bit trials) and removes it before less significant bit conversions, optimizing the balance between DNL error reduction and conversion speed.
Solution Approach 2:
The patent applies dither during some but not all bit trials. Specifically, dither is applied during significant bit trials and removed before less significant bit conversions. This partial action is sufficient to achieve the desired reduction in differential non-linearity errors without the penalty of applying dither throughout the entire conversion process.
Data Source
AI summary
An analog to digital converter comprising a conversion engine having redundancy therein; and a dither device for applying a dither to the conversion engine; and a controller adapted to operate the conversion engine to perform a successive approximation conversion of the analog input, and wherein the dither is removed prior to completion of the analog to digital conversion.