ADC DMA Segmentation for CPU Bus Bandwidth
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Solution Overview
Problem
High-speed analog-digital converters using Direct Memory Access (DMA) transfers can slow or stop CPU operation, reducing system performance, especially when performing continuous conversions of slow-changing variables.
Innovation Solution
An analog-digital converter design that disables DMA access and saves conversion results in local registers, allowing efficient use of data registers and maintaining bus bandwidth, with conversion results from regular and injected groups temporarily stored in single and respective registers, respectively, and transferred to memory through DMA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If DMA access is used to transfer conversion results directly to memory, then silicon area is optimized and only one data register is required, but CPU operation is slowed or stopped and system performance is reduced
Solution Approach 1:
The patent segments the channel conversions into two distinct groups: regular channels and injected channels. This segmentation allows different storage strategies for each group - regular channels use DMA transfer to memory while injected channels store results in local data registers. This resolves the contradiction by allowing DMA to be used selectively for regular channels (optimizing silicon area) while maintaining CPU performance for injected channels that require immediate processing.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the system. Regular channels use DMA transfer with memory storage (optimized for silicon area and bandwidth efficiency), while injected channels use local register storage (optimized for immediate CPU access and processing). This local differentiation allows each subsystem to operate at its optimal performance level without compromising the other.
2Productivity
If DMA access is used for continuous conversions, then conversion results can be transferred to memory, but bus bandwidth is not maintained efficiently and data registers are not optimized
Solution Approach 1:
By segmenting channels into regular and injected groups, the patent enables selective DMA transfer for regular channels while keeping injected channel results in local registers. This segmentation allows the bus to maintain bandwidth for injected channel data access while DMA handles regular channel transfers, optimizing both continuous conversion capability and bus bandwidth utilization.
Solution Approach 2:
The patent introduces local data registers as an intermediary storage mechanism for injected channels. These registers act as a buffer between the ADC and CPU, allowing immediate access to injected channel results without consuming bus bandwidth. The DMA mechanism serves as an intermediary for regular channels, handling bulk transfers to memory while preserving bus availability for other operations.
Data Source
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AI summary
Analog-digital converter device for converting an analog signal into a digital signal. The device comprises: - a first configuration register (ADC_RSQR) for configuring a first group of channels, wherein the conversion result of the channels of the first group is transferred to a memory via a direct memory access, and - a second configuration register (ADC_JSQR) for configuring a second group of channels, wherein each channel of said second group of channels has associated a respective data register, and wherein the conversion results of the channels of the second group are stored in the respective data registers.