Time-Interleaved ADC Clock Duty Control for Idle-Time Utilization
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Solution Overview
Problem
Conventional analog-to-digital conversion circuits have fixed sampling and conversion times, leading to idle time that is not utilized to enhance performance.
Innovation Solution
Analog-to-digital conversion circuits with adjustable duty cycles and buffer circuits that dynamically adjust current based on conversion completion signals to optimize sampling and conversion times, using control circuits to adjust operating clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sampling time and conversion time are fixed in conventional ADC circuits, then the circuit operation is simple and stable, but the idle time cannot be utilized to enhance circuit performance
Solution Approach 1:
The patent implements dynamic adjustment of the operating clock duty cycle based on conversion completion status. When conversion completes early, the duty cycle is increased to utilize idle time for additional operations, thereby enhancing circuit performance without requiring a completely redesign of the fixed-timing architecture
Solution Approach 2:
The patent employs feedback mechanisms where the completion status of ADC conversion is detected and used to control the duty cycle adjustment of the operating clock. This closed-loop control enables the system to adaptively optimize performance by utilizing idle time when conversion completes early, while maintaining stability when conversion takes the full allocated time
2Use of energy by moving object
If the duty cycle of the operating clock is dynamically adjusted, then the power efficiency and linearity are improved, but the control circuit complexity increases
Solution Approach 1:
The patent changes the duty cycle parameter of the operating clock dynamically based on conversion completion status. By adjusting this single critical parameter, the system achieves improved power efficiency and linearity without requiring complex architectural changes, as the adjustment is based on simple completion detection rather than complex real-time optimization algorithms
Solution Approach 2:
The patent prepares the duty cycle adjustment in advance by having the control circuit ready to modify the operating clock parameters once conversion completion is detected. This preliminary preparation of control logic allows for smooth transitions and avoids adding complex real-time decision-making circuits during operation
3Speed
If the buffer circuit current is increased to enhance driving capability, then the ADC can drive the conversion faster, but the power consumption increases
Solution Approach 1:
The patent dynamically adjusts the buffer circuit current based on the duty cycle of the operating clock. When the duty cycle is increased to utilize idle time, the buffer current is proportionally increased to maintain driving capability. This dynamic coordination ensures that power consumption is optimized by matching the current level to the actual operational demand rather than maintaining a constantly high current level
Solution Approach 2:
The patent employs periodic adjustment of buffer circuit current synchronized with the operating clock cycles. The current is increased during active conversion periods and reduced during idle periods, creating a periodic pattern that matches the operational requirements and reduces average power consumption while maintaining conversion speed when needed
Data Source
AI summary
An analog-to-digital conversion circuit that converts an input signal into a digital signal includes a buffer circuit, a switch, an analog-to-digital converter (ADC), and a control circuit. The buffer circuit is configured to receive the input signal and generate an intermediate voltage. The switch is configured to sample the intermediate voltage according to an operating clock to generate a voltage. The ADC is configured to convert the voltage into the digital signal according to the operating clock and generate an indication signal. The control circuit is configured to adjust a duty cycle of the operating clock according to the indication signal and a reference clock. The indication signal indicates that the ADC has completed an analog-to-digital conversion operation.