ADC Dynamic Power Circuit for Low-Power Track-and-Hold Conversion
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Solution Overview
Problem
Analog to digital converters (ADCs) waste power during the track mode as subcircuits like amplifiers and comparators consume power without producing a change in output, leading to inefficiency.
Innovation Solution
Implementing a dynamic power circuit that limits current in ADC subcircuits during the track mode and increases it during the hold mode to reduce power consumption, using a power control device to manage power distribution based on operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the ADC operates in track mode with full power to amplifiers and comparators, then signal tracking accuracy is maintained, but power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by making the power consumption of ADC subcircuits variable rather than fixed. A power control device dynamically adjusts the power supplied to amplifiers and comparators based on the operational mode (track or hold), enabling the system to optimize between accuracy and power consumption in real-time根据不同工作模式自适应调整功耗
Solution Approach 2:
The patent applies local quality by differentiating power management for different ADC subcircuits and operational phases. During track mode, full power is supplied to amplifiers and comparators to maintain signal tracking accuracy, while during hold mode, reduced power is sufficient since no signal processing is needed. This localized power optimization resolves the contradiction between maintaining measurement precision and reducing overall power consumption
2Use of energy by moving object
If the ADC reduces power to subcircuits during track mode, then power consumption decreases, but signal tracking capability deteriorates
Solution Approach 1:
The patent applies periodic action by alternating between two distinct power states corresponding to track and hold modes. The power control device periodically switches power delivery to amplifiers and comparators based on the current operational phase, ensuring full power is available during track mode for accurate signal following, while reducing power during hold mode when signal processing is complete. This periodic power adjustment maintains reliability during critical tracking phases while optimizing power consumption overall
3Speed
If the ADC maintains full power during hold mode, then conversion speed is improved, but power efficiency deteriorates
Solution Approach 1:
The patent applies partial action by providing just the necessary power for each operational mode rather than continuous full power. During hold mode, reduced power is sufficient since the signal has already been captured during track mode and only needs to be held steady. The power control device supplies partial power during hold mode, eliminating the waste of excessive power while maintaining adequate conversion speed for the hold phase operations
Data Source
AI summary
In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.