ADC Dynamic Power Circuit for Low-Power Track-and-Hold
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Analog to digital converters (ADCs) waste power during the track mode as subcircuits like amplifiers and comparators consume power without producing output changes, leading to inefficiency.
Innovation Solution
Implementing a dynamic power circuit that limits current in ADC subcircuits during the track mode and adjusts power accordingly between track and hold modes to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the ADC operates in track mode with full power to amplifiers and comparators, then the signal tracking accuracy is maintained, but power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by making the ADC circuitry switchable between active and low-power states. The track-and-hold circuit dynamically transitions between track mode (full power) and hold mode (reduced power), allowing the system to adapt its power consumption based on operational requirements while maintaining signal integrity when needed.
Solution Approach 2:
The patent implements periodic action through clocked operation where the ADC alternates between track mode and hold mode in regular intervals. During track mode, the circuit operates at full power to accurately follow the input signal, then switches to hold mode where power is reduced while maintaining the sampled value, creating a periodic pattern of high and low power states that reduces average power consumption.
2Use of energy by moving object
If the ADC limits power during track mode, then power consumption is reduced, but the ability to accurately track the input signal deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the ADC operation into distinct phases: track mode for signal acquisition and hold mode for signal maintenance. This segmentation allows the system to concentrate full power during the brief track phase when accuracy is critical, then switch to low-power mode during the hold phase, thereby achieving both power reduction and maintained accuracy through temporal separation of functions.
Solution Approach 2:
The patent implements preliminary action by completing the signal tracking operation in advance during the track mode before transitioning to hold mode. The track-and-hold circuit captures and stores the signal value during track mode when full power is available, preparing the signal for subsequent conversion during hold mode when power is reduced, thus ensuring accuracy is achieved before power reduction occurs.
3Measurement precision
If the ADC uses full power during both track and hold modes, then conversion accuracy is maintained, but power efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by implementing a dynamic power management system that adjusts power consumption based on the operational mode. The ADC transitions between high-power track mode and low-power hold mode, dynamically optimizing the balance between conversion accuracy and power efficiency. This dynamic approach allows the system to maintain accuracy when needed while improving power efficiency through reduced consumption during the hold phase.
Solution Approach 2:
The patent implements parameter changes by varying the power supply voltage or current to the amplifiers and comparators based on the operational mode. During track mode, full power parameters are used to ensure accurate signal following, while during hold mode, reduced power parameters are applied to improve efficiency. This parameter variation allows the ADC to optimize both accuracy and power efficiency across different operational phases.
Data Source
AI summary
In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.