ADC Quantization Error Duplication for Faster Noise Shaping
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Solution Overview
Problem
Noise-shaping analog-to-digital converters (ADCs) face reduced operation speed due to the need for additional phases to sample and integrate quantization error, which interrupts the operation of the switched capacitor array.
Innovation Solution
The use of two additional switched capacitor arrays that operate alternatively to duplicate quantization error, allowing concurrent sampling and integration, thereby increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an additional buffer and integrator are used to sample and integrate quantization error, then the noise-shaping function is improved, but the operation speed of the ADC is reduced
Solution Approach 1:
The switched capacitor array is divided into multiple independent sub-arrays (first, second, third arrays). Each sub-array can independently sample the input signal and generate quantization error, allowing parallel processing of different signal components. This segmentation enables the system to maintain noise-shaping functionality while avoiding the speed penalty of sequential processing.
Solution Approach 2:
By using multiple switched capacitor arrays that operate in parallel, the system ensures continuous sampling and quantization without interruption. While one array is being used for quantization, another array can simultaneously perform sampling and integrator updates, eliminating idle phases and maintaining continuous useful action throughout the conversion process.
2Reliability
If the switched capacitor array and quantizer stop working during integrator operation, then the integrator function is maintained, but the overall ADC operation speed is reduced
Solution Approach 1:
The switched capacitor array is segmented into multiple independent sub-arrays. This allows the system to separate the functions of sampling, quantization, and integration across different arrays, enabling them to operate concurrently without mutual interference or required stoppages.
Solution Approach 2:
Multiple switched capacitor arrays perform preliminary sampling and quantization in parallel before the integration phase. This preliminary action is completed in advance by different arrays, so when integration occurs, the main arrays are already prepared and can continue their normal operation without stopping.
Data Source
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AI summary
The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.