Time-Interleaved ADC Error Correction With Adaptive Frequency Hopping
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face frequency-dependent interleaving errors due to mismatches in parallel sub-ADCs, which existing technologies have not effectively addressed, leading to inaccuracies in signal conversion.
Innovation Solution
A multiple-input multiple-output (MIMO) filter is employed, comprising a delay line, selectors, multiplexers, product generators, and an adder, which generates correction signals to address timing and gain mismatches by estimating errors and using QR-decomposition for coefficient generation, enabling continuous data conversion during ADC clock frequency switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel sub-ADCs are used in time-interleaved configuration, then sampling rate and productivity are improved, but interleaving errors and measurement precision deteriorate due to timing and gain mismatches
Solution Approach 1:
The patent implements feedback mechanisms where the output of each sub-ADC is fed back through correction filters that adjust for timing and gain mismatches. The system continuously monitors and corrects interleaving errors by comparing actual outputs with expected values, applying corrective feedback to maintain precision while preserving the high sampling rate capability of the parallel configuration.
Solution Approach 2:
The patent dynamically adjusts parameters such as timing offsets and gain factors for each sub-ADC channel based on detected interleaving errors. By changing these parameters in real-time through adaptive correction algorithms, the system compensates for mismatches between parallel sub-ADCs, thereby maintaining measurement precision without sacrificing the productivity benefits of the time-interleaved architecture.
2Measurement precision
If correction filters are added to correct interleaving errors, then signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the correction function into separate segments for each sub-ADC channel, with individual correction filters processing outputs from specific sub-ADCs. This segmentation allows for modular implementation where each filter handles a portion of the correction task, making the overall complex system more manageable and enabling parallel processing of corrections without requiring a monolithic complex filter structure.
Solution Approach 2:
The patent introduces intermediary correction filters that act as mediators between the parallel sub-ADCs and the final output combination. These intermediary filters process and correct signals from individual sub-ADCs before they are combined, simplifying the overall correction architecture by breaking down the complex correction task into manageable intermediate steps rather than requiring direct complex processing of all channels simultaneously.
3Measurement precision
If ADC clock frequency is switched to avoid unwanted signals, then signal purity is improved, but data conversion continuity is disrupted
Solution Approach 1:
The patent implements preliminary action by pre-planning and pre-scheduling clock frequency switches to occur during predetermined time intervals when no critical data conversion is expected. The system prepares correction filters and adjustment parameters in advance of frequency switches, ensuring that continuity disruptions are minimized and that the system is ready to resume accurate conversions immediately after each frequency change to maintain signal purity.
Solution Approach 2:
The patent employs periodic clock frequency switching at strategically chosen intervals to avoid unwanted signals while maintaining overall data conversion continuity. By implementing periodic frequency changes rather than continuous or random switching, the system creates predictable patterns that allow for proper synchronization and minimization of disruptions, ensuring signal purity is maintained without excessive interruption of the data conversion process.
Data Source
AI summary
Methods and apparatus for blind detection and correction of interleaving errors using all-digital processing of data output by multiple sub-ADCs of a time-interleaved ADC are disclosed. The methods and apparatus detect and correct frequency-dependent timing and gain mismatches of the sub-ADCs of the time-interleaved ADC using a novel multiple-input multiple-output (MIMO) filter structure. Additionally, a novel adaptive sampling frequency hopping scheme is proposed to achieve uninterrupted data conversion by the time-interleaved ADC during transient time of ADC clock frequency switching.