Pipelined ADC Error Estimation Using Patterns and PRBS Signals
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Solution Overview
Problem
RF sampling ADCs with high sampling rates face significant settling and memory errors due to the open-loop amplifier structure of residue amplifiers, leading to performance degradation across devices and varying temperatures.
Innovation Solution
An analog-to-digital converter (ADC) design that includes a flash ADC, error correction block, selector block, digital-to-analog converter (DAC), residue amplifier, and residual ADC, which uses a known pattern and pseudo-random binary sequence (PRBS) signals to measure and correct for gain, memory, and mismatch errors, allowing for error correction in both startup and steady-state modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If an open-loop residue amplifier structure is used to minimize power consumption, then power consumption is reduced, but settling errors and memory errors increase significantly
Solution Approach 1:
The patent applies preliminary action by performing error measurement and correction during startup mode before normal operation begins. The system measures gain errors, memory errors, and mismatch errors using known test patterns, then stores correction values that are applied during steady-state operation to compensate for the inherent errors in the open-loop amplifier structure.
Solution Approach 2:
The patent implements feedback by measuring actual errors during startup using known input patterns and feedback signals, then using these measurements to adjust and correct the ADC operation during steady-state mode. The correction values derived from startup measurements are applied to compensate for settling and memory errors in real operation.
2Speed
If multiple pipelined ADCs are used to achieve high sampling rates, then sampling rate is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple error correction functions into a unified startup mode measurement process. By combining gain error measurement, memory error measurement, and mismatch error measurement into a single initialization phase using known patterns, the system simplifies the overall device architecture while maintaining high sampling rates through the pipelined structure.
3Measurement precision
If error correction is performed during both startup and steady-state modes, then measurement precision is improved, but test time and power-up time increase
Solution Approach 1:
The patent performs all necessary error measurements and corrections during startup mode before normal operation begins. By completing gain error measurement, memory error measurement, and mismatch error measurement in advance using known test patterns, the system eliminates the need for continuous error correction during steady-state operation, thereby reducing overall test time while maintaining high measurement precision.
Data Source
AI summary
In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.