Differential ADC Feedback Calibration for Common-Mode Rejection
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Solution Overview
Problem
Biopotential reading systems face challenges in dealing with differential DC offset and achieving high common-mode rejection, particularly in power-constrained applications like Body Area Networks, where existing solutions such as high-pass filtering and high-resolution ADCs are inefficient due to high power consumption and slow response times.
Innovation Solution
A circuit and method for automatic common-mode rejection calibration using an analog input stage, analog-digital-converter, and digital-analog-converter in a feedback path to adapt and compensate the DC offset, along with sigma-delta converters for efficient power management and noise reduction, allowing for quasi-pseudo-random calibration signals to balance the circuit operation point and enhance common-mode rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-pass filtering is used to eliminate DC offset, then the DC component can be removed, but the response time becomes very slow and startup is delayed
Solution Approach 1:
The patent measures and stores the DC circuit conditions before disturbances occur, so that when motional artifacts or abrupt variations happen, the pre-stored conditions can be immediately retrieved and applied without waiting for slow filter response. This preliminary measurement and storage of DC conditions enables instant compensation rather than gradual filtering.
2Measurement precision
If high-resolution ADC is used to convert both DC and AC components, then the signal can be captured accurately, but the power consumption increases
Solution Approach 1:
The patent segments the signal processing into two separate paths: a high-resolution path for DC offset measurement and storage, and a lower-resolution path for AC biopotential signal conversion. By dividing the ADC functionality and using different resolution requirements for different signal components, the overall power consumption is reduced while maintaining measurement precision for the useful AC signals.
Solution Approach 2:
The patent discards the DC component after it has been measured and stored, then recovers it later when needed for compensation. Instead of continuously converting and processing the DC component through a high-resolution ADC, the system measures it once, stores the value, and uses it for offset compensation, thereby avoiding continuous high-power consumption while maintaining measurement accuracy.
3Reliability
If symmetrical circuit is used to reduce common-mode effect, then the common-mode rejection can be improved, but the DC difference causes unbalance in operation point
Solution Approach 1:
The patent uses feedback by continuously monitoring the DC offset conditions and adjusting the circuit operation point accordingly. The measured DC conditions are fed back to the circuit to compensate for unbalance, allowing the symmetrical circuit to maintain both common-mode rejection and operation point stability through active correction rather than relying solely on passive symmetry.
Data Source
AI summary
The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (101), an analog-digital-converter (106) for converting an analog signal (107) into its digital representation (108), a digital block (105) arranged to adapt said digital representation (108) of a portion of a DC offset of said analog input signal (101) in accordance with whether said analog input signal (101) is in a predetermined input range of said analog-digital-converter (106), and a digital-analog-converter (103) arranged in a feedback path (102) from said digital block (105) to subtraction means (111) of said analog input stage for converting a digital signal (104) into an analog output signal (109), wherein said analog output signal (109) is subtracted from said analog input signal (101) resulting in said analog signal (107).