Coarse-Incremental ADC Correction for Feedback Error Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converter (ADC) systems, particularly those combining coarse and incremental ADCs, face accuracy deficiencies due to numerical errors from feedback in joint conversion, especially in signal regions with variations from coarse conversion.
Innovation Solution
An ADC system comprising a coarse ADC and an incremental ADC with a feedback path, a decimation filter, and a correction block that generates a correction word to improve accuracy by approximating and compensating for numerical errors, reducing the number of integration cycles and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a coarse ADC and incremental ADC are combined for analog-to-digital conversion, then the conversion range and resolution are improved, but numerical errors occur due to feedback from the joint combination
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing correction values in a lookup table before the actual conversion process. The correction block retrieves and applies these pre-computed values to compensate for numerical errors that would otherwise occur during the feedback-based joint conversion of coarse and incremental ADCs.
Solution Approach 2:
The correction block acts as an intermediary between the coarse ADC/incremental ADC combination and the final output. It introduces a correction mechanism that mediates the numerical errors generated by the feedback path, using pre-calculated correction values to adjust the combined conversion result.
2Measurement precision
If the incremental ADC performs fine conversion iteratively with multiple integration cycles, then the conversion accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent applies partial action by performing only a limited number of integration cycles in the incremental ADC instead of exhaustive iterations. The correction block compensates for the remaining accuracy requirements using pre-calculated correction values, thereby reducing the number of power-consuming integration cycles while maintaining overall conversion accuracy.
Solution Approach 2:
The patent uses a lookup table that stores pre-calculated correction values, essentially creating a copy of the correction data that can be quickly retrieved and applied without performing additional power-intensive calculations during the conversion process.
3Use of energy by moving object
If the number of integration cycles is reduced to lower power consumption, then the energy efficiency is improved, but the conversion accuracy deteriorates
Solution Approach 1:
The correction block serves as an intermediary that compensates for the accuracy loss resulting from reduced integration cycles. It applies pre-calculated correction values to the output of the coarse and incremental ADCs, thereby restoring the accuracy that would otherwise be lost due to fewer integration cycles.
Solution Approach 2:
The patent changes the parameter of integration cycle count from a high value (which consumes more power) to a lower value (which saves power), and compensates for the resulting accuracy change by applying correction values from the lookup table, thus maintaining overall conversion accuracy while reducing power consumption.
Data Source
Figure 1~3
Figure 4
AI summary
An ADC system comprises a coarse ADC for determining a coarse word (CW) representing an input signal, and an incremental ADC (IADC) for determining a fine word (FW) based on a combination of the input signal and a feedback signal. A first combiner (CMB1) generates a first intermediate output word (IW1) by joining the coarse word (CW) and the fine word (FW). A feedback path generates the feedback signal based on the first intermediate output word (IW1). A decimation filter (DEC) generates a second intermediate output word (IW2) by filtering the first intermediate output word (IW1). A correction block (FCAL) determines a correction word (CALW) based on the coarse word (CW), on the first and the second predetermined number of bits and conversion parameters of the incremental ADC. A second combiner generates an output word (OW) by addition of the second intermediate output word (IW2) and the correction word (CALW).