ADC Comparator-DAC Feedback for High-Speed Resolution
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) for 5G wireless systems face challenges in achieving sufficient resolution due to noise and offset issues, high power consumption, and stringent input capacitance requirements, while flash-ADCs and delta-sigma modulators have limitations in speed and resolution trade-offs.
Innovation Solution
A feedback technique where each comparator circuit is directly connected to a digital-to-analog converter (DAC), with the DAC's output connected to the comparator's input, utilizing a statistical flash-ADC with a feedback loop to linearize the transfer characteristic and relax noise constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash-ADC with 2^N - 1 comparators is used to achieve high speed conversion, then conversion speed is improved, but noise and offset requirements become exponentially more stringent and power consumption increases
Solution Approach 1:
The patent divides the high-resolution conversion task into multiple stages: a first flash-ADC performs coarse conversion with fewer comparators, and a second flash-ADC performs fine conversion. This segmentation reduces the number of comparators needed in each stage while maintaining overall high resolution, thereby reducing noise and offset requirements and power consumption.
Solution Approach 2:
The patent introduces an offset compensation circuit as an intermediary component that measures and compensates for comparator offsets. This mediator eliminates the accumulation of offset errors that would otherwise occur in direct high-resolution flash-ADC designs, allowing the use of fewer comparators with relaxed offset requirements.
2Measurement precision
If statistical flash-ADC with Gaussian distribution of offsets is used, then resolution is improved, but non-linearity of Gaussian transfer function must be addressed through calibration or post-distortion
Solution Approach 1:
The patent implements a feedback mechanism where the offset compensation circuit continuously measures the actual offsets of comparators and adjusts compensation signals in real-time. This feedback approach automatically linearizes the transfer function without requiring external calibration or post-distortion processing, reducing device complexity while maintaining high resolution.
Solution Approach 2:
The offset compensation circuit performs self-calibration by measuring its own offset errors and generating compensating signals. This self-service mechanism eliminates the need for external calibration equipment or post-processing distortion correction, simplifying the overall system while achieving linear transfer characteristics.
3Measurement precision
If delta-sigma modulators are used to achieve higher resolution, then resolution is improved, but conversion speed is reduced
Solution Approach 1:
The patent segments the conversion process into parallel flash-ADC stages rather than using sequential delta-sigma modulation. This allows simultaneous coarse and fine conversions to occur in parallel, maintaining high speed while achieving high resolution through the combined output of multiple comparators.
Solution Approach 2:
The patent replaces the feedback-based delta-sigma modulation mechanism with a direct parallel comparison mechanism. Instead of using integrators and feedback loops that limit speed, the invention uses direct flash-ADC comparison with offset compensation, substituting the mechanical feedback system with a direct measurement approach that achieves both high speed and high resolution.
Data Source
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AI summary
An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (105l-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).