Interleaved ADC Filtering With Memory Preload for Chopping Settling

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Solution Overview

Problem

Analog-to-digital converter (ADC) circuits experience reduced data throughput due to chopping techniques, which increase settling time and reduce effective data output rate, particularly in delta-sigma modulator-based systems with Sinc decimation filters, as a result of periodic chopping phases and the need for full settling of filter outputs.

Innovation Solution

The implementation of a method that preloads selectable memory circuits in the filter with reference data, allowing for the combination of sampled input data with preloaded reference data to generate filter outputs, effectively reducing the settling time and maintaining data throughput at unchopped rates by utilizing past states and preloading techniques across multiple stages of the filter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If chopping is used to reduce DC voltage bias, then voltage offset is cancelled, but settling time of the filter is increased

Engineering Contradiction:

Improvevoltage offset cancellationVSAvoidsettling time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by preloading the filter memory circuits with reference data from previous chop phases before the current chop phase completes. This allows the filter to have data ready for immediate output generation, effectively overlapping the settling process with the chopping operation and reducing the apparent settling time without compromising offset cancellation performance

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If chopping is used to eliminate DC bias, then offset voltage is reduced, but effective data throughput is reduced by factor N

Engineering Contradiction:

ImproveDC bias eliminationVSAvoiddata throughput rate

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent implements continuity of useful action by continuously generating filter outputs during the chopping process rather than waiting for complete settling. The filter memory circuits are continuously updated with new samples while simultaneously being read out to generate outputs, maintaining continuous productive operation throughout the chopping cycles

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

By preloading the filter memory with reference data from previous chop phases, the system has data prepared in advance for immediate use in output generation. This eliminates idle waiting time and maintains continuous data throughput equivalent to unchopped configurations

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10236905B1Time interleaved filtering in analog-to-digital converters

Publication Date: 2019.03.19 ANALOG DEVICES GLOBAL UNLTD

AI summary

Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.