Interleaved ADC Gain Mismatch Correction for Chopping Interference
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Solution Overview
Problem
Interleaved sub-ADC circuitries in ADC circuitry suffer from gain mismatch between direct and cross switches, leading to interference and degraded noise spectral density due to manufacturing variations, which complicates the distinction of input signals from interleaving tones.
Innovation Solution
The sub-ADC circuitry estimates the gain differences between direct and cross switches, determines an amplitude difference, and applies a correction value to adjust the quantized signal, mitigating gain mismatch and improving noise spectral density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple sub-ADC circuitries are interleaved to achieve high speed radio frequency sampling, then the sampling speed and bandwidth are improved, but gain mismatch between direct and cross switches introduces interference that degrades noise spectral density
Solution Approach 1:
The patent applies preliminary calibration to detect and store gain mismatch values between direct and cross switches before normal ADC operation. By pre-characterizing the gain differences and storing correction factors in lookup tables, the system prepares compensation data in advance, allowing the main ADC circuitry to operate at high speed without being burdened by real-time calibration computations.
Solution Approach 2:
The patent implements feedback mechanisms where calibration signals are passed through the interleaved sub-ADC circuitries, and the output is compared with expected values to detect gain mismatch. The detected mismatch information is then fed back to adjust calibration factors and correction values, creating a closed-loop system that continuously optimizes performance while maintaining high sampling speeds.
2Measurement precision
If calibration is applied to correct gain and offset mismatches, then measurement precision is improved, but device complexity increases due to additional calibration circuitry and procedures
Solution Approach 1:
The patent enables the ADC system to perform self-calibration by using internal calibration signals and built-in comparison logic. The calibration circuitry uses the ADC's own output to detect mismatches and generate correction factors without requiring external calibration equipment or complex external testing setups, thereby improving precision while limiting complexity growth.
Solution Approach 2:
The patent creates simplified digital models or lookup tables that represent the gain and offset characteristics of each sub-ADC channel. Instead of implementing complex real-time correction circuitry, the system uses pre-computed correction values stored in memory, which are applied during normal operation to achieve precision comparable to complex analog correction circuits.
3Measurement precision
If chopping is applied to mitigate DC content mixing, then signal distinction capability is improved, but gain mismatch between direct and cross switches during switching introduces interference
Solution Approach 1:
The patent introduces calibration signals as intermediary test inputs that are specifically designed to pass through the chopping circuitry and switching mechanisms. These calibration signals enable separate measurement of gain mismatch introduced by the switches during chopping operation, allowing the system to characterize and correct switch-related interference without affecting normal signal processing.
Solution Approach 2:
The patent performs preliminary characterization of the chopping switches by measuring their gain mismatch using calibration signals before normal operation. The measured switch characteristics are stored and used to pre-compute correction factors that compensate for the interference introduced during actual chopped signal processing, thereby maintaining signal distinction capability while reducing switch-induced interference.
Data Source
AI summary
An analog-to-digital converter (ADC) circuitry includes channels that are interleaved with each other to generate output digital signals from input analog signals. A first channel includes sub-ADC circuitry, amplitude detection circuitry, and correction circuitry. Random chopping is applied by chopping circuitry at the input of the sub-ADC circuitry while sampling. The sub-ADC circuitry outputs digital data corresponding to the chopping states. Gain mismatch within the chopping circuitry is mitigated by determining correction values via the amplitude detection circuitry and the correction circuitry and applying the correction values to the output of the sub-ADC circuitry. The amplitude detection circuitry determines an amplitude difference between data signals. The correction circuitry is coupled to the output of the amplitude detection circuitry. The correction circuitry generates the correction values based on the amplitude difference, and outputs the correction values to adjust the data signals.