ADC Gain And Phase Control Using Multiple Channel Estimates

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Solution Overview

Problem

In recording systems, the existing methods for adjusting the amplitude and phase of signals input to analog-to-digital converters (ADCs) are inefficient, leading to quantization noise, saturation, and performance degradation due to underutilization of ADC dynamic range and phase drift during data acquisition and tracking.

Innovation Solution

The system employs multiple channel pulse response estimates with gain and phase constraints to adjust ADC parameters, using a variable-gain amplifier and phase interpolator to optimize signal scaling and sampling, enabling improved loop consistency between acquisition and tracking stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If existing methods for adjusting amplitude and phase of ADC input signals are used, then the system is simple to operate, but quantization noise increases and ADC dynamic range is underutilized

Engineering Contradiction:
Improvesignal resolutionVSAvoidadjustment system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback loops that continuously monitor ADC output signals and adjust VGA gain and phase interpolator settings accordingly. The system uses the ADC output to generate control signals that feed back to the VGA and phase interpolator, creating closed-loop control for optimal signal scaling and phase alignment, thereby improving signal resolution without excessive complexity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent replaces manual or open-loop mechanical adjustment mechanisms with electronic feedback control systems. Instead of fixed or manually adjusted amplitude and phase controls, the system uses electronically controlled VGA and phase interpolator circuits governed by feedback algorithms, achieving precise control through electronic means rather than mechanical adjustment

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Stability of the object's composition

If existing phase adjustment methods are used, then the device structure is simple, but phase drift occurs during data acquisition and tracking

Engineering Contradiction:
Improvesampling phase stabilityVSAvoidphase control structure
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent employs feedback loops that continuously monitor the phase of ADC output signals during data acquisition and tracking operations. The phase interpolator is controlled by feedback from phase detection circuits that compare the actual phase with the desired phase, automatically correcting phase drift without requiring complex external phase control structures

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The phase control system uses the ADC output signals themselves to generate the control signals needed for phase correction. The system is self-regulating, using its own output to control its input phase alignment, thereby maintaining phase stability without external intervention or overly complex control structures

Inventive Principle:
Principle #25Self-service

3Reliability

If ADC parameters are not optimized, then the system is easier to operate, but saturation and performance degradation occur

Engineering Contradiction:
ImproveADC performance consistencyVSAvoidparameter adjustment complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent implements feedback control that automatically adjusts ADC parameters including VGA gain and phase interpolator settings based on real-time monitoring of ADC output signals. The feedback loops detect saturation conditions and performance degradation, automatically correcting parameters to maintain optimal operation without requiring manual intervention

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The ADC parameter optimization system uses the ADC output signals to automatically control the VGA and phase interpolator settings. The system self-regulates by using its own output to generate control signals that optimize its input parameters, maintaining reliable performance without external control or complex manual adjustment procedures

Inventive Principle:
Principle #25Self-service

4Productivity

If transient periods between acquisition and tracking are reduced, then productivity improves, but loop consistency becomes difficult to maintain

Engineering Contradiction:
Improvedata acquisition speedVSAvoidloop consistency
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent implements a unified feedback control architecture that serves both acquisition and tracking functions with the same basic circuitry and control algorithms. The VGA and phase interpolator are controlled by a single feedback system that adapts its operation mode based on whether the system is in acquisition or tracking, eliminating the need for separate control loops and maintaining consistency during transitions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The feedback control system dynamically adapts its behavior based on the operational state (acquisition or tracking). The same feedback loops automatically adjust their control parameters and response characteristics to maintain loop consistency during transitions between acquisition and tracking modes, enabling rapid switching without sacrificing stability

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10483999B1Loop consistency using multiple channel estimates
Publication Date: 2019.11.19 SEAGATE TECH LLC
  • US10483999B1 patent drawing
  • US10483999B1 patent drawing
  • US10483999B1 patent drawing

AI summary

An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.