ADC Gain Calibration Using Three-State Random Signal Injection

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Solution Overview

Problem

Existing methods for calibrating the gain of analog to digital converters (ADCs), particularly in half-integer bit stages, are limited in their ability to effectively calibrate and prevent overload, leading to inefficiencies in processing and extraction of gain calibration.

Innovation Solution

A method involving a random number generator that generates a calibration signal with three possible values (+1, 0, -1) to adjust the digital signal, allowing for effective calibration across the full range of the ADC and preventing overload at the outermost sub-ranges by constraining values in these ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a two-state calibration signal (+1 or -1) is used in existing ADC calibration methods, then the calibration process can be implemented, but the ADC cannot effectively utilize its full range and may experience overload at outermost sub-ranges

Engineering Contradiction:
Improvecalibration accuracyVSAvoidADC range utilization
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The calibration signal is changed from a two-state signal (+1, -1) to a three-state signal (+1, 0, -1). This parameter change allows the calibration signal to represent three different sub-ranges, enabling the ADC to effectively utilize its full range including outermost sub-ranges without overload, while maintaining calibration accuracy

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If background calibration is performed using external equipment, then calibration can be done during manufacturing, but it requires expensive external calibration equipment and additional connection time

Engineering Contradiction:
Improvegain calibrationVSAvoidcalibration system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The ADC system performs its own calibration using an internal random number generator to produce the calibration signal. This self-service approach eliminates the need for expensive external calibration equipment and additional connection time, while achieving accurate gain calibration through the three-state calibration method

Inventive Principle:
Principle #25Self-service

3Extent of automation

If the calibration signal is added to the digital signal from ADC, then the calibration can be performed in the digital domain, but the extraction of gain calibration becomes less efficient

Engineering Contradiction:
Improveautomatic calibrationVSAvoidcalibration extraction efficiency
Core Design Contradiction:
Extent of automationVSProductivity

Solution Approach 1:

By using a three-state calibration signal instead of two-state, the patent enables more efficient extraction of gain calibration data. The additional state provides more information for accurate gain measurement, improving productivity in calibration extraction while maintaining automatic calibration capability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8487792B2Method of gain calibration of an ADC stage and an ADC stage
Publication Date: 2013.07.16 INTEGRATED DEVICE TECH INC
  • US8487792B2 patent drawing
  • US8487792B2 patent drawing
  • US8487792B2 patent drawing

AI summary

A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.