ADC Gray-Code Latching to Prevent Bit Inconsistency
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Solution Overview
Problem
Existing CMOS image sensors face bit inconsistency issues due to the need for a mask signal to control the acquisition of the carry signal, complicating the circuit configuration and design of the analog-digital converter.
Innovation Solution
An analog-digital converter is configured with a comparator, a low-order bit latch section that latches Gray code data using the comparator's output inversion as a trigger, and a high-order bit counter that counts edges of a control signal, stopping high-order bit counting upon comparator output inversion, eliminating the need for a mask signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mask signal is used to control the acquisition of the carry signal, then bit inconsistency can be managed, but the circuit configuration and design become complicated
Solution Approach 1:
The patent extracts and eliminates the mask signal from the circuit by redesigning the timing relationship between the carry signal generation and the low-order bit latching. The carry signal is now acquired at a timing that naturally avoids bit inconsistency without requiring additional mask signal control logic, thereby simplifying the circuit configuration while maintaining bit consistency.
Solution Approach 2:
Instead of using a mask signal to control when the carry signal is acquired, the patent inverts the approach by controlling the latching timing of the low-order bit to coincide with the natural generation timing of the carry signal. This inversion eliminates the need for the mask signal and its associated control logic.
2Use of energy by moving object
If the low-order bit latch section latches counter data, then current consumption is reduced, but bit inconsistency may occur between latched data and carry signal
Solution Approach 1:
The patent applies preliminary action by ensuring that the low-order bit latch section is triggered to latch the counter data at a precisely controlled timing just before or at the moment the carry signal becomes valid. This preliminary timing control ensures that the latched data and the carry signal are bit-consistent while maintaining the low current consumption benefit of latching.
3Productivity
If high-order bit counter section uses binary counter, then subtraction processing is prompt and circuit size is reduced, but bit inconsistency issues arise
Solution Approach 1:
The patent introduces a timing control mechanism as an intermediary between the binary counter and the latching operation. This intermediary ensures that the latching of low-order bits and the generation of the carry signal are synchronized, mediating the potential bit inconsistency while preserving the speed advantages of the binary counter for subtraction processing.
Data Source
AI summary
To simplify the circuit configuration and design of an analog-digital converter. A low-order bit latch section latches, as low-order bits, Gray code data corresponding to a reference clock by using, as a trigger, inversion of an output of a comparator. A high-order bit counter section counts one or both of edges of a CNT signal corresponding to the reference clock and stops a count of high-order bits by using, as a trigger, inversion of an output of the comparator.