Interleaved ADC Harmonic Calibration Using an Attenuated Reference Path
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high-speed, high-resolution analog-to-digital converters (ADCs) suffer from second and third harmonic distortion (HD2 and HD3) errors due to nonlinearities in analog sampling, which limit their dynamic range and are not effectively corrected by current digital calibration methods, especially in highly-interleaved ADCs.
Innovation Solution
Incorporating a reference ADC channel with attenuated input to generate error codes, and using a correlation-code sign-counting method to digitally detect and correct HD2 and HD3 errors by adjusting coefficients through a low-complexity least-mean-squares update process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital calibration methods are used to correct harmonic distortion errors, then measurement precision is improved, but device complexity increases due to additional correction circuits and algorithms
Solution Approach 1:
The patent creates a simplified copy of the ADC system by generating synthetic reference signals that mirror the expected linear response. These reference signals are processed through the same signal path to create a comparison model, enabling error detection without requiring complex external calibration equipment or additional correction circuits beyond the basic ADC structure.
Solution Approach 2:
The ADC system performs self-calibration by using its own output signals to generate reference signals for comparison. The system extracts fundamental frequency components from its own output, reconstructs expected linear responses, and compares these against actual measurements to automatically detect and correct harmonic distortion errors internally.
2Manufacturing precision
If complex digital calibration algorithms are implemented, then manufacturing precision is improved, but loss of time increases due to extended calibration procedures
Solution Approach 1:
The patent performs calibration actions in advance by generating reference signals and comparing them against actual ADC outputs during normal operation. The system pre-computes expected linear responses using synthetic sine wave generation and accumulates error measurements over time, so that calibration is continuously performed rather than requiring separate calibration sessions.
Solution Approach 2:
The calibration process operates continuously during normal ADC operation rather than requiring periodic interruptions. The system continuously generates reference signals, compares them with actual outputs, and updates correction coefficients in real-time, ensuring constant improvement of linearity accuracy without stopping the conversion process.
3Measurement precision
If memory resources are increased to store calibration data, then measurement precision is improved, but device complexity increases due to additional memory components
Solution Approach 1:
The patent stores calibration data locally within the signal processing pipeline rather than in separate memory components. Error measurements and correction coefficients are maintained in registers and buffers that are tightly integrated with the signal processing logic, allowing fast access without requiring external memory or large storage arrays.
Solution Approach 2:
The calibration data structures are nested within the existing ADC control and processing logic. Reference signal generation, error measurement accumulation, and correction coefficient storage are all embedded within the normal operation control flow, eliminating the need for separate memory modules and reducing overall device complexity.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.