Programmable-Gain ADC Input Circuit With Common-Mode Current Nulling
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Solution Overview
Problem
Discrete-time analog-to-digital converter (ADC) input circuits face challenges in handling large common-mode voltage differences, requiring buffering and external common-mode references, which increase power consumption and complexity, while maintaining high impedance and low thermal noise injection.
Innovation Solution
A delta-sigma ADC circuit with a switching mechanism that charges a reference feedback capacitor with respect to the common-mode voltage, couples it to the input terminal, and discharges it to maintain the summing node at common-mode voltage, thereby reducing signal current and eliminating the need for external buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the input sampling capacitor is made large to reduce thermal noise, then thermal noise is reduced, but the input impedance decreases
Solution Approach 1:
The patent employs periodic switching of the reference feedback capacitor between charging and discharging states synchronized with clock phases. This periodic action allows the capacitor to maintain a small average capacitance while effectively canceling input voltage through repeated charge transfer cycles, thereby reducing thermal noise without requiring a large continuous capacitance that would lower input impedance.
Solution Approach 2:
The patent implements feedback by coupling the reference feedback capacitor between the input terminal and the summing node, using the quantizer output to control the charging voltage. This feedback mechanism allows the system to dynamically adjust the capacitor voltage to cancel the input voltage, achieving noise reduction through controlled charge transfer rather than relying on large passive capacitance.
2Difficulty of detecting and measuring
If buffering stages are added to handle common-mode voltage differences, then high input impedance is maintained, but power consumption increases
Solution Approach 1:
The patent makes the reference feedback capacitor serve multiple functions: it acts as both the feedback element for the integrator and as the input sampling capacitor. By charging this capacitor to the common-mode voltage of the input terminal and then coupling it to the input, the system eliminates the need for separate buffering stages, achieving high input impedance without additional power-consuming buffers.
Solution Approach 2:
The reference feedback capacitor is designed to perform multiple roles within the circuit. It functions as the feedback capacitor for the integrator, as the input sampling capacitor during the charge phase, and as the element that cancels common-mode voltage. This multi-functionality removes the need for dedicated buffering circuitry, reducing overall power consumption while maintaining high input impedance.
3Adaptability or versatility
If external common-mode voltage reference and buffering are used, then common-mode voltage handling is improved, but device complexity increases
Solution Approach 1:
The patent extracts the common-mode voltage handling function from external circuits and integrates it directly into the reference feedback capacitor charging mechanism. By charging the capacitor to the common-mode voltage of the input terminal and using it for feedback, the system eliminates external common-mode voltage references and associated buffering circuitry, reducing device complexity while maintaining adaptability to common-mode voltage variations.
4Object-affected harmful factors
If the input sampling capacitor is increased to reduce thermal noise, then thermal noise is reduced, but additional buffering is required
Solution Approach 1:
The patent uses periodic switching of the reference feedback capacitor in synchronization with clock phases to achieve effective input sampling. This periodic charging and discharging allows the capacitor to maintain a small size while effectively canceling input voltage through repeated charge transfer, reducing thermal noise without requiring a large continuous capacitance that would necessitate additional buffering.
Solution Approach 2:
The system employs feedback control where the quantizer output determines the charging voltage of the reference feedback capacitor. This feedback mechanism enables dynamic voltage cancellation at the input terminal, achieving thermal noise reduction through active control rather than passive large capacitance, thereby eliminating the need for additional buffering stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a high-input impedance with low power consumption, reducing thermal noise and eliminating the need for external common-mode references, allowing for programmable gain without additional buffering.
Implementation Method 1
A switching circuit charges a reference feedback capacitor(s) to a quantizer-dependent reference feedback voltage with respect to the common-mode voltage of the reference
Implementation Method 2
the switching circuit couples the reference feedback capacitor(s) between the input terminal and the summing node of an integrator that provides the first stage of the delta-sigma ADC loop filter, thereby applying the reference feedback voltage to cancel the input voltage
Implementation Method 3
The switching circuit discharges the reference feedback capacitor(s) in a third clock phase, so that voltages dependent on the input terminal voltage that are present at the end of the second clock phase, are removed
Data Source
AI summary
A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using one or more reference capacitor(s) that have been charged with a net charge corresponding to a quantizer-controlled reference voltage in a preceding clock phase. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high input impedance. The reference capacitor(s) may be discharged in a third clock phase, so that input-signal-dependent voltages are discharged from the capacitor(s). An additional sampling capacitor can be discharged in the first clock phase and coupled in parallel with the reference capacitor during the second clock phase, to set the gain with respect to the input voltage.