ADC Input Circuit With Level Shifting for Low Input Charge
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Solution Overview
Problem
Conventional analog to digital converters with rail to rail buffers consume excessive on-chip area and power, especially at high sampling rates, making them costly for applications with multiple analog input sources.
Innovation Solution
The proposed input circuit for analog to digital converters employs channel selection switches and level shifting circuitry to minimize the charge transferred to the sampling capacitor, reducing the voltage drop across the input filter and thereby increasing the sampling rate without the need for large rail to rail buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If rail to rail buffers are used to sample the input voltage, then the input charge is eliminated and sampling rate can be increased, but the on-chip area and power consumption become excessively large
Solution Approach 1:
The patent extracts only the essential function of sampling the input voltage without requiring full rail-to-rail buffering. By removing the excessive buffering capability and keeping only the necessary sampling function, the circuit achieves high sampling rates while dramatically reducing power consumption and on-chip area.
Solution Approach 2:
Instead of using large buffers to actively drive the sampling capacitor, the patent inverts the approach by using a small buffer that charges the sampling capacitor to a voltage slightly above the input voltage, then using a switch to transfer the signal. This inverted approach reduces the buffering requirement while maintaining sampling performance.
2Productivity
If rail to rail buffers are used to sample the input voltage, then the input charge is eliminated and sampling rate can be increased, but the on-chip area becomes excessively large
Solution Approach 1:
The patent extracts only the essential function of sampling the input voltage without requiring full rail-to-rail buffering. By removing the excessive buffering capability and keeping only the necessary sampling function, the circuit achieves high sampling rates while dramatically reducing power consumption and on-chip area.
Solution Approach 2:
Instead of using large buffers to actively drive the sampling capacitor, the patent inverts the approach by using a small buffer that charges the sampling capacitor to a voltage slightly above the input voltage, then using a switch to transfer the signal. This inverted approach reduces the buffering requirement while maintaining sampling performance.
3Reliability
If conventional analog to digital conversion with rail to rail buffers is used, then input charge concerns are eliminated, but power consumption and area cost become too high for applications with numerous analog input sources
Solution Approach 1:
The patent extracts only the essential function of sampling the input voltage without requiring full rail-to-rail buffering. By removing the excessive buffering capability and keeping only the necessary sampling function, the circuit achieves high sampling rates while dramatically reducing power consumption and on-chip area.
Solution Approach 2:
The patent introduces an intermediary switching mechanism that transfers the sampled voltage from the buffer output to the sampling capacitor. This intermediary switch allows the small buffer to effectively drive the sampling capacitor without requiring the buffer to continuously supply charge, thus reducing power consumption while maintaining reliable input charge management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the current flowing from the analog input node to the sampling capacitor, lowering power consumption and on-chip area requirements, while maintaining efficient analog to digital conversion.
Implementation Method 1
a capacitive node connected to the output node. A first control circuit is configured to set a charge at the capacitive node to a desired voltage
Implementation Method 2
A second control circuit is configured to set a charge at the capacitive node to a voltage at the first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node
Data Source
AI summary
A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.