Segmented ADC Input Amplifier for Sample-Rate Power Scaling

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Solution Overview

Problem

ADC input circuits face challenges in optimizing power consumption across a wide range of sample rates, bandwidth, and noise requirements, particularly due to varying slew rate and settling time demands, which complicates design and increases power consumption.

Innovation Solution

The circuit employs a combination of selectively enabled amplifiers with adjustable power consumption, gain, and noise floor, allowing for tailored bandwidth and noise performance based on the selected sample rate, using amplifier slices instead of adjusting bias current to maintain a stable DC operating point.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the bias current of the first amplifier stage is increased to reduce thermal noise and distortion, then the signal-to-noise ratio and distortion levels improve, but the power consumption increases significantly

Engineering Contradiction:

Improvesignal-to-noise ratioVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The first amplifier stage is divided into multiple parallel amplifier circuits (e.g., two or more operational amplifiers) that can be independently enabled or disabled. By segmenting the amplifier functionality, the circuit can activate only the necessary number of amplifiers based on the current sample rate requirements, thereby reducing power consumption while maintaining adequate noise performance. This segmentation allows the system to trade off between noise performance and power consumption dynamically.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If the bias current is reduced to save power at lower sample rates, then power consumption decreases, but the non-linearity and distortion levels increase

Engineering Contradiction:

Improvepower consumptionVSAvoidlinearity

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

By dividing the amplifier functionality into multiple parallel circuits that can be selectively enabled, the system maintains adequate linearity by ensuring that enough amplifiers are active to handle the current signal requirements. Even at reduced power modes, the remaining active amplifiers operate at their full bias current, maintaining their individual linearity characteristics, while the parallel configuration provides sufficient aggregate performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple amplifier circuits are combined in parallel to achieve the required performance. The parallel combination of amplifiers provides both the necessary drive capability and linearity while allowing power consumption to be reduced by disabling unused amplifier paths. The merging of multiple amplifier outputs through a summing node or common output stage maintains signal integrity and linearity.

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by moving object

If the bias current is adjusted over a wide range to optimize power consumption, then power efficiency improves, but the operating point variation increases circuit design complexity

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit design complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Instead of continuously adjusting the bias current of a single amplifier, the system segments the amplifier functionality into discrete parallel circuits that can be independently switched. This approach converts a continuous control problem into a discrete selection problem, simplifying the control logic. The circuit designer only needs to determine which amplifier paths to enable based on sample rate requirements, rather than designing complex bias current adjustment circuitry that maintains stable operating points across wide current ranges.

Inventive Principle:

Principle #1Segmentation

4Speed

If the settling time is decreased to meet high sample rate requirements, then the bandwidth must be increased, but the power consumption increases

Engineering Contradiction:

Improvesample rateVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The amplifier system is segmented into multiple parallel circuits with different bandwidth and power characteristics. At high sample rates, all amplifier circuits are enabled to provide the necessary aggregate bandwidth and reduce settling time. At lower sample rates, fewer amplifier circuits are enabled, reducing power consumption while providing sufficient bandwidth for the relaxed timing requirements. This segmentation allows the system to dynamically match amplifier resources to sample rate demands.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7477178B1Power-optimized analog-to-digital converter (ADC) input circuit

Publication Date: 2009.01.13 CIRRUS LOGIC INC

AI summary

A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth and noise performance level. The selection of the combination of enabled amplifiers may be made in conformity with the sample rate of the converter and the amplifiers may have evenly-weighted bias currents, or unevenly weighed bias currents and may be optimized for their particular use in combinations for bandwidth and 1/f noise corner performance. The outputs of the amplifiers are combined in a combiner circuit, which may be a discrete-time chopping amplifier that receives charges from a plurality of capacitors that sample each enabled amplifier output.