ADC Input Stage Switching for High-Voltage Sampling Accuracy
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Solution Overview
Problem
Analog/digital converters face challenges in accurately converting high voltages due to variations in capacitance ratios and reference voltage offsets, particularly when applying a reference voltage from a lower voltage domain to a higher voltage domain, leading to crosstalk and increased surface area requirements for dedicated input stages.
Innovation Solution
The implementation of a sampled analog/digital converter input stage with a transistor arrangement and switch apparatus that separates voltage domains, allowing for the application of both high input voltages and lower reference voltages without the need for additional input stages, using a switch apparatus to couple the reference voltage to the sampling capacitor arrangement, and a method for testing that determines the capacitance ratio between sampling and digital/analog converter capacitors based on digital values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated input stage is used for high voltage conversion, then conversion accuracy is improved, but device complexity and surface area requirements increase
Solution Approach 1:
The sampling capacitor arrangement is designed to handle both high voltage sampling and reference voltage application functions. The same capacitor arrangement that samples high voltage input signals is also used to store reference voltages for testing and calibration, eliminating the need for separate dedicated input stages for different voltage domains.
Solution Approach 2:
The patent combines the high voltage input path and reference voltage path through a common sampling capacitor arrangement. The switch apparatus selectively connects the sampling capacitor to either the high voltage input or the reference voltage source, merging multiple functions into a single shared infrastructure that reduces overall device complexity.
2Object-affected harmful factors
If separate input stages are used for different voltage domains, then crosstalk is reduced, but surface area requirements increase
Solution Approach 1:
The sampling operation uses periodic switching controlled by a clock signal to alternately connect the sampling capacitor to the high voltage input or to the reference voltage source. This time-division multiplexing approach ensures that high voltage and reference voltage are never present simultaneously on the same node, eliminating crosstalk while using a single shared capacitor that minimizes surface area.
Solution Approach 2:
The patent introduces the time dimension to separate voltage domains that would otherwise require spatial separation. By switching between different voltage sources at different time periods, the system achieves voltage domain isolation without requiring physically separate input stages, thereby reducing surface area requirements.
3Device complexity
If capacitance ratio variations are tolerated, then device complexity is reduced, but conversion accuracy deteriorates
Solution Approach 1:
The patent replaces physical capacitance ratio matching with a digital calibration approach. A test controller applies known reference voltages and measures the resulting digital output codes to calculate actual capacitance ratios. These measured ratios are then used to compute correction factors that compensate for deviations from ideal capacitance ratios, substituting complex physical matching with simpler digital processing.
Solution Approach 2:
The system dynamically adjusts the interpretation of digital output codes based on measured capacitance ratios. Rather than requiring fixed, precisely-matched capacitance values, the system changes the scaling parameters used to convert digital codes to analog voltage values, thereby compensating for capacitance variations and maintaining accuracy without complex hardware matching.
Data Source
AI summary
An input stage for an analog/digital converter, an analog/digital converter and a method for testing analog/digital converters with successive approximation are disclosed. At an input stage, an input signal is supplied via a first transistor arrangement of a sampling capacitor arrangement. The sampling capacitor arrangement can be optionally connected to ground or to a reference voltage by way of a second transistor arrangement and a switch apparatus.