Sigma-Delta ADC Serial Interface with Asynchronous Sampling Clock
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Solution Overview
Problem
Digital isolators used in ADC circuits introduce jitter to the sampling clock, increasing noise and reducing the signal-to-noise ratio, especially at higher frequencies, and require multiple channels that increase costs.
Innovation Solution
An apparatus and method where a master clock signal is generated independently of the digital isolator's serial clock signal, allowing the ADC to produce an asynchronous sampling clock, reducing jitter and channel requirements, and using a three-wire full duplex interface to minimize noise and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital isolator is used to provide translation of digital signals between isolated domains, then isolation between ADC measurement input and digital backend is achieved, but jitter is added to the sampling clock signal which increases noise and reduces signal-to-noise ratio
Solution Approach 1:
The system separates the sampling clock generation from the digital isolator by using an on-chip oscillator in the ADC to generate the sampling clock independently, while the digital isolator only handles data transfer. This segmentation eliminates jitter introduction into the sampling clock while maintaining isolation benefits.
Solution Approach 2:
The sampling clock function is extracted from the digital isolator and placed locally within the ADC circuitry. The oscillator circuit generates the sampling clock signal independently within the ADC, removing the harmful jitter effect that would otherwise be introduced by the digital isolator.
2Reliability
If multiple channels are used in the digital isolator to transfer signals between domains, then complete signal transfer is achieved, but the cost of the digital isolator circuit increases
Solution Approach 1:
The digital isolator is configured to perform multiple functions using fewer channels: it transfers both the conversion result data and control signals (such as conversion start commands) through the same isolation interface. This multi-functionality reduces the number of isolator channels needed while maintaining complete signal transfer capability.
Solution Approach 2:
Multiple signal types (data output, conversion start input, and other control signals) are merged into a single bidirectional communication interface between the ADC and the digital isolator. This combining of functions reduces the channel count requirement and lowers the overall cost of the digital isolator circuit.
3Measurement precision
If the ADC sampling clock is generated from the serial clock signal provided by the digital isolator, then synchronization is achieved, but jitter from the isolator degrades the signal-to-noise ratio especially at higher frequencies
Solution Approach 1:
The system segments the clocking functions by providing separate clock inputs: a master clock for the ADC operation and a serial clock for the digital interface communication. This segmentation allows the ADC to use a clean, isolated master clock for sampling while the serial clock handles only data transfer synchronization, preventing jitter contamination of the sampling process.
Solution Approach 2:
The patent introduces an intermediary asynchronous sample rate converter that bridges the master clock domain and the serial clock domain. This mediator allows the ADC to operate at the precise sampling rate determined by the clean master clock while still maintaining proper data transfer synchronization with the digital isolator through the serial interface, without directly coupling the sampling clock to the jitter-prone serial clock signal.
Data Source
AI summary
An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.