ADC Digital Interface Circuit for Flexible Channel Sequencing
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Solution Overview
Problem
Efficient communication between controllers and analog-to-digital converters (ADCs) in electronic systems is challenging due to resource-intensive data transfer and limited functionality in existing A/D conversion systems, particularly in achieving flexible channel ordering, programmable delays, and channel oversampling.
Innovation Solution
An analog-to-digital conversion system with a digital interface circuit that includes a multiplexer, an ADC, and a digital interface block coupled between the ADC and a processor, which receives and decodes commands to control the ADC operation, supporting flexible channel ordering, programmable delays, and channel oversampling through a FIFO buffer and DMA controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are transferred repeatedly from the processor to the ADC for each conversion sequence, then the ADC can be controlled to perform multiple conversions, but the processor consumes significant resources and time for data transfer
Solution Approach 1:
The patent applies preliminary action by pre-loading a sequence of channel commands into a FIFO buffer before the actual conversion sequence begins. The processor transfers the entire command sequence to the FIFO buffer in advance, and then the ADC autonomously executes the conversions by reading commands from the buffer without requiring repeated processor intervention. This resolves the contradiction by performing the data transfer action beforehand, eliminating repeated transfers during conversion execution.
Solution Approach 2:
The patent introduces a FIFO buffer as an intermediary component between the processor and the ADC. This buffer serves as a mediator that stores the command sequence and allows the ADC to retrieve commands independently without continuous processor involvement. The FIFO buffer decouples the processor from the ADC operation, enabling the processor to initiate conversions and then continue other tasks while the ADC autonomously processes the pre-loaded command sequence from the buffer.
2Ease of operation
If the processor directly controls each ADC conversion operation, then precise control is achieved, but the system complexity and resource consumption increase
Solution Approach 1:
The patent applies segmentation by dividing the control function into two independent parts: the processor generates and transfers the command sequence to the FIFO buffer, and the ADC autonomously reads and executes commands from the buffer. This segmentation separates the control initiation (processor) from the control execution (ADC), reducing the burden on the processor and simplifying the overall control architecture while maintaining precise control through the structured command format in the buffer.
Solution Approach 2:
The patent enables self-service by allowing the ADC to autonomously retrieve commands from the FIFO buffer and execute conversions without continuous processor intervention. Once the command sequence is loaded into the buffer, the ADC independently manages the conversion sequence, channel switching, and timing based on the pre-loaded commands. This self-service capability reduces processor resource consumption and simplifies the control system architecture.
3Adaptability or versatility
If channel conversion sequences are fixed in the ADC, then the device is simpler to manufacture, but flexibility in channel ordering and sequencing is limited
Solution Approach 1:
The patent applies dynamics by making the channel conversion sequence configurable through software commands rather than being fixed in hardware. The FIFO buffer stores a sequence of channel commands that can be programmatically defined to specify any desired conversion order and timing. This dynamic approach allows the same ADC hardware to adapt to different application requirements by loading different command sequences, providing flexibility in channel ordering and sequencing without requiring multiple specialized ADC designs.
Data Source
AI summary
A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.