Flash ADC Interpolating Comparator Array for 1-Bit Resolution

Solution Overview

Problem

Conventional flash analog-to-digital converters (ADCs) face significant increases in complexity, power consumption, and die area for every 1-bit increase in accuracy, making it challenging to enhance conversion accuracy without substantial changes to the analog interface or power consumption.

Innovation Solution

The implementation of a comparator array with primary and interpolating comparators, along with a binary converter, allows for an additional bit of accuracy by interpolating between reference voltages, reducing the need for additional reference levels and maintaining minimal changes to the analog interface and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of static voltage references and comparators is increased by a factor of two to increase ADC accuracy by 1-bit, then measurement precision is improved, but device complexity increases by a factor of two

Engineering Contradiction:

ImproveADC accuracyVSAvoidcomparator array complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The comparator array is segmented into two functional groups: primary comparators that perform standard comparisons against reference voltages, and interpolating comparators that perform interpolation between reference voltages. This segmentation allows the system to achieve higher accuracy without proportionally increasing the total number of comparators, as the interpolating comparators leverage information from multiple primary comparators rather than requiring independent comparison circuits for each accuracy level.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Interpolating comparators act as intermediaries between the primary comparators and the final digital output. These interpolating comparators take inputs from multiple primary comparators and generate interpolated output signals that represent intermediate voltage levels between the reference voltages. This intermediary approach enables the system to achieve finer resolution without directly increasing the number of primary comparison elements.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If the number of static voltage references and comparators is increased by a factor of two to increase ADC accuracy by 1-bit, then measurement precision is improved, but the die area increases by up to a factor of two

Engineering Contradiction:

ImproveADC accuracyVSAvoidADC die area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The comparator array is segmented into two functional groups: primary comparators that perform standard comparisons against reference voltages, and interpolating comparators that perform interpolation between reference voltages. This segmentation allows the system to achieve higher accuracy without proportionally increasing the total number of comparators, as the interpolating comparators leverage information from multiple primary comparators rather than requiring independent comparison circuits for each accuracy level.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interpolating comparators serve multiple functions: they receive inputs from multiple primary comparators, perform interpolation calculations, and generate output signals that contribute to the final high-precision digital code. This multi-functionality allows a single interpolating comparator to replace what would traditionally require multiple separate comparison elements, thereby reducing the overall die area required for achieving high accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If the analog interface circuit drives more comparators to maintain linearity specifications, then measurement precision is improved, but power consumption increases

Engineering Contradiction:

ImproveADC accuracyVSAvoidanalog interface power consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The comparator array is segmented into two functional groups: primary comparators that perform standard comparisons against reference voltages, and interpolating comparators that perform interpolation between reference voltages. This segmentation allows the system to achieve higher accuracy without proportionally increasing the total number of comparators, as the interpolating comparators leverage information from multiple primary comparators rather than requiring independent comparison circuits for each accuracy level.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7561092B2Extension of accuracy of a flash ADC by 1-bit through interpolation of comparator outputs

Publication Date: 2009.07.14 V SILICON SEMICON (HANGZHOU) CO LTD

AI summary

ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.