Two-Tier Sampling Phase Adjustment Using ADC and Digital Interpolation
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Solution Overview
Problem
Current sampling correction frequency circuits in data transfer systems face challenges in achieving sufficient accuracy, especially in low-cost, high-performance environments with reduced signal-to-noise ratios, which affects the accuracy of data sampling and transfer.
Innovation Solution
The implementation of a two-tier sampling phase adjustment circuit that includes an analog to digital converter with coarse control, a digital interpolation circuit with fine control, and a phase error calculation and adjustment mechanism to refine sampling frequencies, allowing for accurate phase adjustments in both the analog and digital domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current sampling correction frequency circuits are used in low-cost, high-performance data transfer systems, then cost is reduced, but measurement precision of sampling phase deteriorates
Solution Approach 1:
The sampling phase correction is divided into two independent tiers: coarse correction that adjusts the ADC sampling clock phase, and fine correction that adjusts the digital interpolation phase. This segmentation allows each tier to operate with simpler, lower-cost circuitry while collectively achieving high precision sampling phase accuracy.
Solution Approach 2:
The invention transitions from a single-domain (analog or digital) correction approach to a two-domain approach by implementing coarse correction in the analog domain (ADC sampling clock) and fine correction in the digital domain (interpolation circuit). This dimensional change enables cost-effective implementation while maintaining high measurement precision.
2Productivity
If higher density data patterns are transferred, then productivity increases, but measurement precision of sampling deteriorates due to reduced signal to noise ratio
Solution Approach 1:
The system continuously monitors the sampling phase error and feeds it back to both the coarse and fine correction circuits. The coarse correction circuit adjusts the ADC sampling clock based on the feedback, while the fine correction circuit adjusts the digital interpolation phase. This dual-feedback mechanism maintains sampling accuracy even when transferring higher density data patterns with reduced signal-to-noise ratio.
3Device complexity
If a single-tier sampling correction circuit is used, then device complexity is reduced, but measurement precision of sampling phase is insufficient
Solution Approach 1:
The correction circuit is segmented into two independent but coordinated tiers: a coarse correction circuit that handles large phase adjustments and a fine correction circuit that handles precise phase adjustments. This segmentation allows each circuit to be relatively simple in structure while their combined operation achieves high sampling phase accuracy that would be difficult to obtain with a single complex circuit.
Solution Approach 2:
The system dynamically switches between coarse and fine correction modes based on the magnitude of phase error. When large phase deviations occur, the coarse correction dominates; when precision is required, the fine correction takes over. This dynamic operation allows the system to maintain high accuracy without requiring both circuits to operate at maximum complexity simultaneously.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.