ADC Clock Jitter Correction via Paired Reference Sampling
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Solution Overview
Problem
High-speed Analog-to-Digital Converters (ADCs) are limited by clock jitter, which introduces noise-like errors into digital signal streams, constraining their dynamic range and Effective Number of Bits (ENOB), especially at higher frequencies where clock jitter significantly impacts ADC performance.
Innovation Solution
A system and process that measure and compensate for clock jitter by obtaining samples of a periodic analog reference signal both with and without jitter, determining the difference, and converting this difference to a digital representation to estimate timing errors, allowing for correction of jitter-induced errors in the digital signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed sampling is implemented in ADCs, then conversion rate is improved, but clock jitter increases causing noise-like errors and reducing dynamic range
Solution Approach 1:
The patent implements a feedback mechanism where the actual sampling instants are measured and used to correct the assumed uniform sampling times. A timing error detector measures the deviation between actual and ideal sampling moments, and this timing error information is fed back to correct the digital signal reconstruction process, thereby compensating for jitter effects at high conversion rates
Solution Approach 2:
The patent replaces the assumption of perfectly uniform mechanical timing with a digital correction system. Instead of relying on ideal clock timing, the system uses digital processing to measure and compensate for timing deviations, substituting the mechanical precision requirement with a digital measurement and correction approach
2Productivity
If higher conversion rates are achieved, then productivity is improved, but timing jitter increases causing loss of information
Solution Approach 1:
The system measures actual sampling timing deviations and feeds this timing error information back to the signal reconstruction process. By using this feedback, the system can correctly interpret samples taken at non-uniform intervals, preventing information loss that would otherwise occur due to timing jitter at high conversion rates
Solution Approach 2:
The patent changes the parameter of sampling time from being assumed uniform to being explicitly measured and corrected. By introducing timing error as a measurable and correctable parameter, the system maintains signal fidelity even when operating at higher conversion rates where timing variations become significant
3Productivity
If clock frequency is increased to improve conversion rate, then productivity is improved, but clock jitter becomes more significant reducing measurement precision
Solution Approach 1:
The patent implements a timing error measurement and feedback system that directly addresses clock jitter. The system measures the actual timing deviations introduced by high-frequency clocks and uses this information to correct the sampling time assumptions in signal reconstruction, thereby maintaining measurement precision despite increased clock frequency
Solution Approach 2:
The patent introduces an intermediary timing error measurement system between the clock and the sampling process. This intermediary measures the clock's timing deviations and provides correction information, acting as a mediator that allows high-frequency operation while maintaining timing accuracy through digital compensation
Data Source
AI summary
Processes and systems for use in reducing clock jitter-induced error, obtain a first sample during each cycle of a periodic analog reference signal. The sample includes an error resulting at least in part from jitter-induced timing error of the clock signal. For each respective cycle, a second sample of a discrete-time analog representation of the periodic analog reference signal is also obtained. The second sample is substantially unsusceptible to jitter-induced timing error of the clock signal. Each of the first and second samples corresponds to the same respective cycle of the clock signal. For each cycle, a respective difference between each of the first and second samples is determined. The difference is indicative of timing error of the respective cycle of the clock signal. The difference is converted to a digital representation that can be used to compensate for jitter-induced error.