Time-Interleaved ADC Clocking With Local Phase Generation
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Solution Overview
Problem
Conventional Analog-to-Digital Converter (ADC) arrays face issues such as delay buffer mismatch, clock routing mismatch, and high routing complexity due to the use of delay matched clock lines, along with difficulties in clock phase distribution and scrambling, which affect the performance of time-interleaved sampling and conversion.
Innovation Solution
A circuit design where a single clock is distributed to all ADCs, enabling local digital phase generation and on-the-fly programmable sampling phases, allowing for random selection and scrambling of ADCs to reduce noise and spurs, with redundant ADCs used for averaging and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If delay matched clock lines are used for time-interleaved sampling, then sampling clock phase distribution is achieved, but delay buffer mismatch and clock routing mismatch occur
Solution Approach 1:
The patent replaces the mechanical/delay-based clock distribution system with a digital phase generation system. Instead of using physical delay buffers and matched clock lines to distribute phases, each ADC generates its own sampling clock phase digitally using a phase generation unit. This substitution eliminates delay buffer mismatch and clock routing mismatch while achieving the required phase distribution for time-interleaved sampling.
2Speed
If multiple delay matched clock lines are used for routing, then clock phase distribution is achieved, but routing complexity increases
Solution Approach 1:
The patent segments the centralized clock distribution function into individual ADC units. Instead of routing multiple clock lines from a central source through complex interconnects, each ADC contains its own phase generation unit that independently generates the required clock phase. This segmentation eliminates complex routing while achieving the same phase distribution effect.
3Productivity
If conventional time-interleaved sampling is used, then high sampling rate is achieved, but spurious components and SFDR degradation occur
Solution Approach 1:
The patent introduces dynamic phase adjustment capability to the time-interleaved sampling system. Each ADC's phase generation unit can dynamically adjust its sampling clock phase, enabling the system to adaptively compensate for mismatches and reduce spurious components. This dynamic adjustment maintains the high sampling rate benefit while eliminating the SFDR degradation caused by fixed phase relationships in conventional time-interleaved sampling.
Data Source
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AI summary
A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.