ADC Channel Grouping With Local Registers to Preserve Bus Bandwidth

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Solution Overview

Problem

High-speed analog-digital converters using Direct Memory Access (DMA) transfers can be slow and may halt CPU operation, reducing system performance, especially when monitoring slow-changing variables.

Innovation Solution

Analog-digital converters are designed to disable DMA access and store conversion results in local registers, allowing efficient use of data registers and maintaining bus bandwidth, with conversion results from regular groups temporarily saved in a single local register and transferred via DMA, while injected group results are saved in respective registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DMA access is enabled for continuous conversions, then conversion results are transferred to memory, but CPU operation may be halted and system performance is reduced

Engineering Contradiction:
Improveconversion result transferVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the data transfer process by introducing a buffer memory that temporarily stores conversion results before DMA transfer to memory. This segmentation allows the system to separate the conversion operation from the transfer operation, preventing CPU halts while ensuring reliable data transfer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a buffer memory as an intermediary between the ADC and the main memory. This intermediary component receives conversion results directly from the ADC via DMA without blocking the CPU, and then transfers data to memory at optimal times, thus maintaining system performance while ensuring reliable data transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If DMA access is used for every conversion, then conversion results are saved in memory, but bus bandwidth is reduced and data register efficiency is lowered

Engineering Contradiction:
Improveconversion result storageVSAvoidbus bandwidth
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the data storage function by introducing a buffer memory that handles temporary storage of conversion results. This allows the system to perform multiple conversions without saturating the bus, as only periodic bulk transfers to main memory are performed rather than individual transfers for each conversion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer memory performs preliminary storage of conversion results before they are transferred to main memory. This preliminary action allows the ADC to continue operating at full speed without waiting for memory transfers, maintaining bus bandwidth while ensuring reliable storage of all conversion results.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8174419B2Analog-digital converter and corresponding system and method
Publication Date: 2012.05.08 STMICROELECTRONICS SRL
  • US8174419B2 patent drawing
  • US8174419B2 patent drawing
  • US8174419B2 patent drawing

AI summary

An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.