ADC Gain and Phase Loop Consistency Using Dual Channel Estimates
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Solution Overview
Problem
In recording systems, the performance is degraded due to underutilization of the dynamic range of analog-to-digital converters (ADCs) and phase drift during signal acquisition and tracking, leading to quantization noise and saturation, which existing systems fail to adequately address through gain and phase adjustments.
Innovation Solution
The system employs multiple channel pulse response estimates with different constraints to adjust the amplitude and phase of the input signal to the ADC, using a variable-gain amplifier and phase interpolator, allowing for effective utilization of the ADC's dynamic range and maintaining phase synchronization during both acquisition and tracking phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single channel pulse response estimation is used for gain adjustment, then the system is simpler, but the ADC dynamic range is underutilized and quantization noise increases
Solution Approach 1:
The patent divides the channel pulse response estimation into two separate estimations: one with a gain constraint and another with a phase constraint. This segmentation allows each estimation to focus on a specific aspect (gain or phase), improving the accuracy of individual parameter estimation while maintaining overall system manageability. The segmented approach enables more precise ADC parameter adjustment without excessive complexity.
Solution Approach 2:
The patent introduces an intermediary mechanism that uses phase-constrained channel pulse response estimation to determine gain control parameters for the VGA. This intermediary approach allows the system to leverage phase information to improve gain adjustment accuracy, thereby optimizing ADC dynamic range utilization and reducing quantization noise without directly complicating the main gain control path.
2Measurement precision
If gain and phase adjustments are made using separate estimations, then ADC dynamic range utilization improves, but the device complexity increases
Solution Approach 1:
The patent merges the results of two separate channel pulse response estimations (gain-constrained and phase-constrained) into a unified control system. The gain estimation result is used for VGA gain control while the phase estimation result informs gain control parameter determination during preamble. This merging allows the system to achieve optimal ADC dynamic range utilization by combining the strengths of both estimations without requiring completely separate control paths, thus managing complexity.
Solution Approach 2:
The channel pulse response estimation circuits are designed to serve multiple functions: the gain-constrained estimation primarily controls VGA gain, while the phase-constrained estimation both controls phase and provides information for gain control parameter determination. This multi-functionality reduces the need for additional dedicated circuits, as each estimation serves more than one purpose, thereby limiting the increase in device complexity while achieving improved ADC dynamic range utilization.
3Reliability
If phase constraint estimation is used for gain control parameter determination, then loop consistency improves, but the calculation complexity increases
Solution Approach 1:
The patent performs phase-constrained channel pulse response estimation during the preamble portion of the signal, before the main data transmission begins. This preliminary action allows the system to determine gain control parameters in advance, ensuring loop consistency is established before critical data processing. By performing this calculation beforehand rather than in real-time during data transmission, the system achieves improved loop consistency without adding ongoing calculation complexity to the main data path.
Data Source
AI summary
An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.


