ADC Capacitor Sampling Layout for Low ISI and Common-Mode Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) suffer from inter-symbol interference (ISI) and instability due to mismatched common-mode voltages between input and reference voltages, leading to poor performance.
Innovation Solution
The proposed ADC design incorporates multiple capacitors and switches to sample input and reference voltages independently, reducing interference and stabilizing the circuit by adjusting reference voltages to match common-mode voltages, thereby minimizing ISI and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacitor alternately receives input voltage and reference voltage, then the ADC performs analog-to-digital conversion, but inter-symbol interference occurs and circuit stability deteriorates
Solution Approach 1:
The patent divides the single capacitor into two separate capacitors (first capacitor and second capacitor). The first capacitor is dedicated to sampling the input voltage, while the second capacitor is dedicated to sampling the reference voltage. This segmentation prevents the reference voltage from interfering with the input voltage sampling, thereby eliminating inter-symbol interference and improving circuit stability.
2Adaptability or versatility
If the common-mode voltage of reference voltage differs from input voltage, then the ADC operates with different voltage levels, but circuit stability deteriorates
Solution Approach 1:
The patent introduces a common-mode voltage adjustment circuit that adjusts the common-mode voltage of the reference voltage to match the common-mode voltage of the input voltage. This creates equipotential conditions between the two voltage sources, preventing instability caused by voltage mismatch while maintaining the ADC's ability to handle different voltage levels.
Data Source
AI summary
The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.