ADC Linearization Circuit With Reconfigurable LUT Calibration
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Solution Overview
Problem
Delay domain ADC topologies suffer from nonlinearity, which is compensated by calibration using known inputs, but this process is affected by noise issues such as DAC flicker noise, impacting accuracy.
Innovation Solution
A nonlinear ADC system with a linearization circuit and a reconfigurable lookup table (LUT) memory that stores initial, intermediate, and updated calibration data to correct nonlinearity, using averaging and interpolation methods to reduce calibration errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If delay domain ADC topology is used, then power consumption and area are reduced, but nonlinearity increases
Solution Approach 1:
The ADC is divided into two separate functional blocks: a nonlinear delay domain ADC core and a linearization circuit with LUT memory. This segmentation allows each block to be optimized independently - the core for low power/area and the linearization circuit for correcting nonlinearity, resolving the contradiction between power efficiency and linearity.
Solution Approach 2:
A linearization circuit acts as an intermediary between the nonlinear delay domain ADC and the digital output. This intermediary block contains a LUT memory that stores calibration data to compensate for the nonlinearity introduced by the delay domain topology, enabling the system to achieve both low power consumption and high linearity.
2Manufacturing precision
If calibration is performed using DAC with known inputs, then nonlinearity is compensated, but noise from DAC flicker affects accuracy
Solution Approach 1:
Calibration is performed in advance during manufacturing or initialization, storing the compensation data in LUT memory before normal operation. This preliminary calibration captures the nonlinear characteristics under controlled conditions, and the stored data is then used during operation without requiring continuous calibration that would be susceptible to DAC flicker noise.
Solution Approach 2:
Instead of continuously using DAC to generate calibration signals during operation, the calibration data is copied into LUT memory during initialization. The LUT then provides the linearization correction during normal operation without requiring the DAC to be active, eliminating the impact of DAC flicker noise on measurement accuracy.
3Manufacturing precision
If LUT memory stores calibration data, then nonlinearity is corrected, but memory area increases
Solution Approach 1:
The LUT memory is implemented as a separate, compact block dedicated solely to storing calibration data. This segmentation allows the memory to be optimized for minimal size while still providing the necessary linearization function, preventing excessive area expansion.
Solution Approach 2:
The LUT memory stores only the essential calibration data needed for linearization, not the entire signal processing function. This localized storage approach minimizes the memory area required while still achieving the goal of nonlinearity correction.
Data Source
AI summary
A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.