ADC Linearization Circuit Using LUT Updates Against Calibration Noise
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Solution Overview
Problem
Analog-to-digital converters (ADCs) with delay domain topology suffer from nonlinearity, which is compensated by calibration using known inputs, but noise during the calibration process, such as DAC flicker noise, affects the accuracy of the calibration.
Innovation Solution
A circuit comprising a nonlinear ADC and a linearization circuit with a lookup table (LUT) memory that stores initial calibration data, where the linearization circuit updates the data based on the initial data to provide a corrected digital output, using methods like averaging and interpolation to reduce calibration errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If calibration is performed using known inputs to compensate for nonlinearity, then linearity is improved, but noise during calibration (e.g., DAC flicker noise) degrades measurement precision
Solution Approach 1:
The patent performs multiple calibration operations in advance and stores the results in a lookup table (LUT) memory. By pre-calculating and storing correction values for various input levels, the system eliminates the need for real-time calibration during normal operation, thereby avoiding the impact of noise present during calibration operations.
Solution Approach 2:
The patent creates multiple copies of the LUT memory structure to store calibration data. Instead of performing single calibration operations, the system performs multiple calibration runs and stores the results in redundant LUT structures, which can then be averaged or selected to produce a final calibration table that is less affected by noise in any single calibration operation.
2Use of energy by moving object
If delay domain ADC topology is used, then power consumption and area are reduced, but nonlinearity increases
Solution Approach 1:
The patent introduces a linearization circuit as an intermediary component between the delay domain ADC and the output. This linearization circuit uses a lookup table (LUT) memory to store pre-calculated correction values that compensate for the nonlinearity inherent in the delay domain topology, thereby maintaining the power and area advantages while achieving linear output characteristics.
Solution Approach 2:
The patent changes the operational parameters of the ADC system by implementing calibration operations that generate correction data. This calibration data is then used to modify the transfer function of the ADC through the linearization circuit, transforming the nonlinear delay domain ADC into an effectively linear device without changing the fundamental delay domain topology.
Data Source
AI summary
A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.