ADC Sense Circuit for Multi-Level Memory Noise Discrimination

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Solution Overview

Problem

Conventional sense amplifiers struggle to accurately read multi-bit memory elements and imaging devices due to noise interference, leading to reduced memory density and image fidelity, as they fail to distinguish small differences in voltage or current levels.

Innovation Solution

A quantizing circuit that samples and filters electrical parameters to reduce noise impact, allowing for the detection of small differences in voltage or current levels, thereby enabling increased data storage per memory element and improved imaging sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional sense amplifiers are used to read multi-bit memory elements, then the memory elements can store more data (higher memory density), but the ability to accurately distinguish small voltage or current level differences deteriorates due to noise interference

Engineering Contradiction:
Improvedata storage capacityVSAvoidvoltage level discrimination accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent segments the sensing process into multiple discrete voltage level comparisons. Instead of attempting to measure continuous analog voltage levels directly, the sense amplifier divides the measurement into segmented steps, comparing the memory element voltage against multiple reference voltage levels sequentially. This segmentation allows accurate discrimination of multi-bit memory elements by determining which reference level the stored voltage falls between, thereby resolving the contradiction between increased data storage capacity and measurement precision.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the number of readable states of the memory element is reduced to avoid noise interference, then measurement accuracy improves, but memory density decreases

Engineering Contradiction:
Improvereading accuracyVSAvoidmemory density
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent implements a feedback mechanism where the sense amplifier uses the output from each voltage comparison to determine the next reference voltage level to compare against. The circuit feedbacks the comparison results to systematically narrow down the voltage range, allowing accurate reading of multiple memory states without being overwhelmed by noise. This feedback approach enables the system to maintain high measurement precision while fully utilizing the multi-state capability of memory elements for high density storage.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If multi-bit memory elements are made increasingly dense, then memory capacity increases, but the voltage difference between levels decreases making them harder to sense

Engineering Contradiction:
Improvememory capacityVSAvoidvoltage level detection difficulty
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies preliminary action by pre-establishing multiple reference voltage levels before the actual sensing operation. These reference levels are prepared in advance and correspond to the boundaries between different multi-bit memory states. During sensing, the memory element voltage is directly compared against these pre-prepared references, eliminating the need for complex real-time calculations and enabling accurate detection even when voltage differences between levels are minimal. This preliminary preparation of reference levels makes high-density multi-bit memory elements detectable despite reduced voltage margins.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8098180B2Devices including analog-to-digital converters for internal data storage locations
Publication Date: 2012.01.17 MICRON TECHNOLOGY INC
  • US8098180B2 patent drawing
  • US8098180B2 patent drawing
  • US8098180B2 patent drawing

AI summary

A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.