ADC Meta-Stability Bit Detection Without Per-Bit Memory

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Solution Overview

Problem

Analog-to-digital converting devices face increased design complexity and error risks due to the need for memories and activation signals to detect meta-stability, which can lead to prolonged comparison times and errors in digital signal output.

Innovation Solution

An analog-to-digital converting device that detects meta-stability using a meta-stability signal and a counter to determine the bit at which meta-stability occurs, without requiring a memory corresponding to each bit of the digital signal, by employing a meta-stability detection unit, counter, and control logic to manage the comparison process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memories and activation signals are used to detect meta-stability, then meta-stability detection capability is improved, but device complexity increases

Engineering Contradiction:
Improvemeta-stability detection capabilityVSAvoiddesign complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the meta-stability detection function from the traditional memory-based approach and implements it using a dedicated meta-stability detection unit that operates directly on comparator outputs. This removes the need for multiple memory units and activation signals, reducing device complexity while maintaining detection capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a meta-stability detection unit as an intermediary component between the comparator and the output logic. This unit processes comparator outputs directly and generates meta-stability signals without requiring memory storage, simplifying the overall system architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If comparison operations are repeated to improve accuracy, then conversion precision is improved, but comparison time increases

Engineering Contradiction:
Improveconversion precisionVSAvoidcomparison time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the meta-stability detection unit continuously monitors comparator outputs and provides feedback signals to control logic. When meta-stability is detected, the system can adjust comparison operations dynamically, allowing repeated comparisons only when necessary to maintain precision without excessive time loss.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the comparison process dynamic by allowing the number and timing of comparison operations to be adjusted based on real-time meta-stability conditions. The system performs repeated comparisons adaptively rather than following a fixed sequence, optimizing both precision and time efficiency.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12088317B2Analog to digital converting device and operating method thereof
Publication Date: 2024.09.10 SAMSUNG ELECTRONICS CO LTD
  • US12088317B2 patent drawing
  • US12088317B2 patent drawing
  • US12088317B2 patent drawing

AI summary

An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.